ARM Ltd. Musca_S1 2025.07.04 ARM 32-bit v8-M Mainline based device CM33 r0p1 little true 3 false 8 32 CODE_SRAM_MPC Code SRAM Memory Protection Controller MPC 0x50130000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index Register 0x10 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 32 bit[3_0] Block size 0 4 CTRL MPC Control Register 0x0 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 32 bit[4] Security error response configuration 4 5 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 7 bit[7] Data interface gating acknowledge (RO) 7 8 bit[8] Auto-increment 8 9 INT_CLEAR Interrupt clear 0x24 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 17 bit[17] cfg_ns 17 18 INT_SET Interrupt set. Debug purpose only 0x34 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 CPU0CORE_PPU CPU0 Core Power Policy Unit PPU 0x50023000 0x0 0x1000 registers n AIDR Architecture Identification Register 0xFCC read-only n 0x0 0xFFFFFFFF AIMR Additional Interrupt Mask Register 0x34 read-write n 0x0 0xFFFFFFFF AISR Additional Interrupt Status Register 0x3C read-write n 0x0 0xFFFFFFFF DCDR0 Device Control Delay Configuration Register 0 0x170 read-write n 0x0 0xFFFFFFFF DCDR1 Device Control Delay Configuration Register 1 0x174 read-write n 0x0 0xFFFFFFFF DISR Device Interface Input Current Status Register 0x10 read-only n 0x0 0xFFFFFFFF EDTR0 Power Mode Entry Delay Register 0 0x160 read-write n 0x0 0xFFFFFFFF EDTR1 Power Mode Entry Delay Register 1 0x164 read-write n 0x0 0xFFFFFFFF FULRR Full Retention RAM Configuration Register 0x54 read-write n 0x0 0xFFFFFFFF FUNRR Functional Retention RAM Configuration Register 0x50 read-write n 0x0 0xFFFFFFFF IDR0 PPU Identification Register 0 0xFB0 read-only n 0x0 0xFFFFFFFF IDR1 PPU Identification Register 1 0xFB4 read-only n 0x0 0xFFFFFFFF IESR Input Edge Sensitivity Register 0x40 read-write n 0x0 0xFFFFFFFF IIDR Implementation Identification Register 0xFC8 read-only n 0x0 0xFFFFFFFF IMR Interrupt Mask Register 0x30 read-write n 0x0 0xFFFFFFFF ISR Interrupt Status Register 0x38 read-write n 0x0 0xFFFFFFFF MEMRR Memory Retention RAM Configuration Register 0x58 read-write n 0x0 0xFFFFFFFF MISR Miscellaneous Input Current Status Register 0x14 read-only n 0x0 0xFFFFFFFF OPSR Operating Mode Active Edge Sensitivity Register 0x44 read-write n 0x0 0xFFFFFFFF PMER Power Mode Emulation Register 0x4 read-write n 0x0 0xFFFFFFFF PTCR Power Mode Transition Configuration Register 0x24 read-write n 0x0 0xFFFFFFFF PWCR Power Configuration Register 0x20 read-write n 0x0 0xFFFFFFFF PWPR Power Policy Register 0x0 read-write n 0x0 0xFFFFFFFF PWSR Power Status Register 0x8 read-only n 0x0 0xFFFFFFFF STSR Stored Status Register 0x18 read-only n 0x0 0xFFFFFFFF UNLK Unlock Register 0x1C read-write n 0x0 0xFFFFFFFF CPU0DBG_PPU CPU0 Debug Power Policy Unit PPU 0x50024000 0x0 0x1000 registers n AIDR Architecture Identification Register 0xFCC read-only n 0x0 0xFFFFFFFF AIMR Additional Interrupt Mask Register 0x34 read-write n 0x0 0xFFFFFFFF AISR Additional Interrupt Status Register 0x3C read-write n 0x0 0xFFFFFFFF DCDR0 Device Control Delay Configuration Register 0 0x170 read-write n 0x0 0xFFFFFFFF DCDR1 Device Control Delay Configuration Register 1 0x174 read-write n 0x0 0xFFFFFFFF DISR Device Interface Input Current Status Register 0x10 read-only n 0x0 0xFFFFFFFF EDTR0 Power Mode Entry Delay Register 0 0x160 read-write n 0x0 0xFFFFFFFF EDTR1 Power Mode Entry Delay Register 1 0x164 read-write n 0x0 0xFFFFFFFF FULRR Full Retention RAM Configuration Register 0x54 read-write n 0x0 0xFFFFFFFF FUNRR Functional Retention RAM Configuration Register 0x50 read-write n 0x0 0xFFFFFFFF IDR0 PPU Identification Register 0 0xFB0 read-only n 0x0 0xFFFFFFFF IDR1 PPU Identification Register 1 0xFB4 read-only n 0x0 0xFFFFFFFF IESR Input Edge Sensitivity Register 0x40 read-write n 0x0 0xFFFFFFFF IIDR Implementation Identification Register 0xFC8 read-only n 0x0 0xFFFFFFFF IMR Interrupt Mask Register 0x30 read-write n 0x0 0xFFFFFFFF ISR Interrupt Status Register 0x38 read-write n 0x0 0xFFFFFFFF MEMRR Memory Retention RAM Configuration Register 0x58 read-write n 0x0 0xFFFFFFFF MISR Miscellaneous Input Current Status Register 0x14 read-only n 0x0 0xFFFFFFFF OPSR Operating Mode Active Edge Sensitivity Register 0x44 read-write n 0x0 0xFFFFFFFF PMER Power Mode Emulation Register 0x4 read-write n 0x0 0xFFFFFFFF PTCR Power Mode Transition Configuration Register 0x24 read-write n 0x0 0xFFFFFFFF PWCR Power Configuration Register 0x20 read-write n 0x0 0xFFFFFFFF PWPR Power Policy Register 0x0 read-write n 0x0 0xFFFFFFFF PWSR Power Status Register 0x8 read-only n 0x0 0xFFFFFFFF STSR Stored Status Register 0x18 read-only n 0x0 0xFFFFFFFF UNLK Unlock Register 0x1C read-write n 0x0 0xFFFFFFFF CPU1CORE_PPU CPU1 Core Power Policy Unit PPU 0x50025000 0x0 0x1000 registers n AIDR Architecture Identification Register 0xFCC read-only n 0x0 0xFFFFFFFF AIMR Additional Interrupt Mask Register 0x34 read-write n 0x0 0xFFFFFFFF AISR Additional Interrupt Status Register 0x3C read-write n 0x0 0xFFFFFFFF DCDR0 Device Control Delay Configuration Register 0 0x170 read-write n 0x0 0xFFFFFFFF DCDR1 Device Control Delay Configuration Register 1 0x174 read-write n 0x0 0xFFFFFFFF DISR Device Interface Input Current Status Register 0x10 read-only n 0x0 0xFFFFFFFF EDTR0 Power Mode Entry Delay Register 0 0x160 read-write n 0x0 0xFFFFFFFF EDTR1 Power Mode Entry Delay Register 1 0x164 read-write n 0x0 0xFFFFFFFF FULRR Full Retention RAM Configuration Register 0x54 read-write n 0x0 0xFFFFFFFF FUNRR Functional Retention RAM Configuration Register 0x50 read-write n 0x0 0xFFFFFFFF IDR0 PPU Identification Register 0 0xFB0 read-only n 0x0 0xFFFFFFFF IDR1 PPU Identification Register 1 0xFB4 read-only n 0x0 0xFFFFFFFF IESR Input Edge Sensitivity Register 0x40 read-write n 0x0 0xFFFFFFFF IIDR Implementation Identification Register 0xFC8 read-only n 0x0 0xFFFFFFFF IMR Interrupt Mask Register 0x30 read-write n 0x0 0xFFFFFFFF ISR Interrupt Status Register 0x38 read-write n 0x0 0xFFFFFFFF MEMRR Memory Retention RAM Configuration Register 0x58 read-write n 0x0 0xFFFFFFFF MISR Miscellaneous Input Current Status Register 0x14 read-only n 0x0 0xFFFFFFFF OPSR Operating Mode Active Edge Sensitivity Register 0x44 read-write n 0x0 0xFFFFFFFF PMER Power Mode Emulation Register 0x4 read-write n 0x0 0xFFFFFFFF PTCR Power Mode Transition Configuration Register 0x24 read-write n 0x0 0xFFFFFFFF PWCR Power Configuration Register 0x20 read-write n 0x0 0xFFFFFFFF PWPR Power Policy Register 0x0 read-write n 0x0 0xFFFFFFFF PWSR Power Status Register 0x8 read-only n 0x0 0xFFFFFFFF STSR Stored Status Register 0x18 read-only n 0x0 0xFFFFFFFF UNLK Unlock Register 0x1C read-write n 0x0 0xFFFFFFFF CPU1DBG_PPU CPU1 Debug Power Policy Unit PPU 0x50026000 0x0 0x1000 registers n AIDR Architecture Identification Register 0xFCC read-only n 0x0 0xFFFFFFFF AIMR Additional Interrupt Mask Register 0x34 read-write n 0x0 0xFFFFFFFF AISR Additional Interrupt Status Register 0x3C read-write n 0x0 0xFFFFFFFF DCDR0 Device Control Delay Configuration Register 0 0x170 read-write n 0x0 0xFFFFFFFF DCDR1 Device Control Delay Configuration Register 1 0x174 read-write n 0x0 0xFFFFFFFF DISR Device Interface Input Current Status Register 0x10 read-only n 0x0 0xFFFFFFFF EDTR0 Power Mode Entry Delay Register 0 0x160 read-write n 0x0 0xFFFFFFFF EDTR1 Power Mode Entry Delay Register 1 0x164 read-write n 0x0 0xFFFFFFFF FULRR Full Retention RAM Configuration Register 0x54 read-write n 0x0 0xFFFFFFFF FUNRR Functional Retention RAM Configuration Register 0x50 read-write n 0x0 0xFFFFFFFF IDR0 PPU Identification Register 0 0xFB0 read-only n 0x0 0xFFFFFFFF IDR1 PPU Identification Register 1 0xFB4 read-only n 0x0 0xFFFFFFFF IESR Input Edge Sensitivity Register 0x40 read-write n 0x0 0xFFFFFFFF IIDR Implementation Identification Register 0xFC8 read-only n 0x0 0xFFFFFFFF IMR Interrupt Mask Register 0x30 read-write n 0x0 0xFFFFFFFF ISR Interrupt Status Register 0x38 read-write n 0x0 0xFFFFFFFF MEMRR Memory Retention RAM Configuration Register 0x58 read-write n 0x0 0xFFFFFFFF MISR Miscellaneous Input Current Status Register 0x14 read-only n 0x0 0xFFFFFFFF OPSR Operating Mode Active Edge Sensitivity Register 0x44 read-write n 0x0 0xFFFFFFFF PMER Power Mode Emulation Register 0x4 read-write n 0x0 0xFFFFFFFF PTCR Power Mode Transition Configuration Register 0x24 read-write n 0x0 0xFFFFFFFF PWCR Power Configuration Register 0x20 read-write n 0x0 0xFFFFFFFF PWPR Power Policy Register 0x0 read-write n 0x0 0xFFFFFFFF PWSR Power Status Register 0x8 read-only n 0x0 0xFFFFFFFF STSR Stored Status Register 0x18 read-only n 0x0 0xFFFFFFFF UNLK Unlock Register 0x1C read-write n 0x0 0xFFFFFFFF CRYPTO_PPU Crypto Power Policy Unit PPU 0x50027000 0x0 0x1000 registers n AIDR Architecture Identification Register 0xFCC read-only n 0x0 0xFFFFFFFF AIMR Additional Interrupt Mask Register 0x34 read-write n 0x0 0xFFFFFFFF AISR Additional Interrupt Status Register 0x3C read-write n 0x0 0xFFFFFFFF DCDR0 Device Control Delay Configuration Register 0 0x170 read-write n 0x0 0xFFFFFFFF DCDR1 Device Control Delay Configuration Register 1 0x174 read-write n 0x0 0xFFFFFFFF DISR Device Interface Input Current Status Register 0x10 read-only n 0x0 0xFFFFFFFF EDTR0 Power Mode Entry Delay Register 0 0x160 read-write n 0x0 0xFFFFFFFF EDTR1 Power Mode Entry Delay Register 1 0x164 read-write n 0x0 0xFFFFFFFF FULRR Full Retention RAM Configuration Register 0x54 read-write n 0x0 0xFFFFFFFF FUNRR Functional Retention RAM Configuration Register 0x50 read-write n 0x0 0xFFFFFFFF IDR0 PPU Identification Register 0 0xFB0 read-only n 0x0 0xFFFFFFFF IDR1 PPU Identification Register 1 0xFB4 read-only n 0x0 0xFFFFFFFF IESR Input Edge Sensitivity Register 0x40 read-write n 0x0 0xFFFFFFFF IIDR Implementation Identification Register 0xFC8 read-only n 0x0 0xFFFFFFFF IMR Interrupt Mask Register 0x30 read-write n 0x0 0xFFFFFFFF ISR Interrupt Status Register 0x38 read-write n 0x0 0xFFFFFFFF MEMRR Memory Retention RAM Configuration Register 0x58 read-write n 0x0 0xFFFFFFFF MISR Miscellaneous Input Current Status Register 0x14 read-only n 0x0 0xFFFFFFFF OPSR Operating Mode Active Edge Sensitivity Register 0x44 read-write n 0x0 0xFFFFFFFF PMER Power Mode Emulation Register 0x4 read-write n 0x0 0xFFFFFFFF PTCR Power Mode Transition Configuration Register 0x24 read-write n 0x0 0xFFFFFFFF PWCR Power Configuration Register 0x20 read-write n 0x0 0xFFFFFFFF PWPR Power Policy Register 0x0 read-write n 0x0 0xFFFFFFFF PWSR Power Status Register 0x8 read-only n 0x0 0xFFFFFFFF STSR Stored Status Register 0x18 read-only n 0x0 0xFFFFFFFF UNLK Unlock Register 0x1C read-write n 0x0 0xFFFFFFFF DBG_PPU Debug Power Policy Unit PPU 0x50029000 0x0 0x1000 registers n AIDR Architecture Identification Register 0xFCC read-only n 0x0 0xFFFFFFFF AIMR Additional Interrupt Mask Register 0x34 read-write n 0x0 0xFFFFFFFF AISR Additional Interrupt Status Register 0x3C read-write n 0x0 0xFFFFFFFF DCDR0 Device Control Delay Configuration Register 0 0x170 read-write n 0x0 0xFFFFFFFF DCDR1 Device Control Delay Configuration Register 1 0x174 read-write n 0x0 0xFFFFFFFF DISR Device Interface Input Current Status Register 0x10 read-only n 0x0 0xFFFFFFFF EDTR0 Power Mode Entry Delay Register 0 0x160 read-write n 0x0 0xFFFFFFFF EDTR1 Power Mode Entry Delay Register 1 0x164 read-write n 0x0 0xFFFFFFFF FULRR Full Retention RAM Configuration Register 0x54 read-write n 0x0 0xFFFFFFFF FUNRR Functional Retention RAM Configuration Register 0x50 read-write n 0x0 0xFFFFFFFF IDR0 PPU Identification Register 0 0xFB0 read-only n 0x0 0xFFFFFFFF IDR1 PPU Identification Register 1 0xFB4 read-only n 0x0 0xFFFFFFFF IESR Input Edge Sensitivity Register 0x40 read-write n 0x0 0xFFFFFFFF IIDR Implementation Identification Register 0xFC8 read-only n 0x0 0xFFFFFFFF IMR Interrupt Mask Register 0x30 read-write n 0x0 0xFFFFFFFF ISR Interrupt Status Register 0x38 read-write n 0x0 0xFFFFFFFF MEMRR Memory Retention RAM Configuration Register 0x58 read-write n 0x0 0xFFFFFFFF MISR Miscellaneous Input Current Status Register 0x14 read-only n 0x0 0xFFFFFFFF OPSR Operating Mode Active Edge Sensitivity Register 0x44 read-write n 0x0 0xFFFFFFFF PMER Power Mode Emulation Register 0x4 read-write n 0x0 0xFFFFFFFF PTCR Power Mode Transition Configuration Register 0x24 read-write n 0x0 0xFFFFFFFF PWCR Power Configuration Register 0x20 read-write n 0x0 0xFFFFFFFF PWPR Power Policy Register 0x0 read-write n 0x0 0xFFFFFFFF PWSR Power Status Register 0x8 read-only n 0x0 0xFFFFFFFF STSR Stored Status Register 0x18 read-only n 0x0 0xFFFFFFFF UNLK Unlock Register 0x1C read-write n 0x0 0xFFFFFFFF DUALTIMER Dual Timer Timer 0x40002000 0x0 0x3C registers n DUALTIMER Dual Timer 5 TIMER1BGLOAD Timer 1 Background Load Register 0x18 read-write n 0x0 0xFFFFFFFF TIMER1CONTROL Timer 1 Control Register 0x8 read-write n 0x20 0xFFFFFFFF InterruptEnable Interrupt Enable bit 5 1 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 OneShotCount Selects one-shot or wrapping counter mode 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerEnable Timer Enable Enable bit 7 1 Disable Timer is disabled 0 Enable Timer is enabled 1 TimerMode Timer Mode bit 6 1 Free-Running Free-Running timer mode 0 Periodic Periodic timer mode 1 TimerPre Timer prescale bits 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 TimerSize Selects 16-bit or 32- bit counter operation 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TIMER1INTCLR Timer 1 Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear TIMER1LOAD Timer 1 Load Register 0x0 read-write n 0x0 0xFFFFFFFF TIMER1MIS Timer 1 Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Timer Interrupt 0 1 TIMER1RIS Timer 1 Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw Timer Interrupt 0 1 TIMER1VALUE Timer 1 Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF TIMER2BGLOAD Timer 2 Background Load Register 0x38 read-write n 0x0 0xFFFFFFFF TIMER2CONTROL Timer 2 Control Register 0x28 read-write n 0x20 0xFFFFFFFF InterruptEnable Interrupt Enable bit 5 1 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 OneShotCount Selects one-shot or wrapping counter mode 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerEnable Timer Enable Enable bit 7 1 Disable Timer is disabled 0 Enable Timer is enabled 1 TimerMode Timer Mode bit 6 1 Free-Running Free-Running timer mode 0 Periodic Periodic timer mode 1 TimerPre Timer prescale bits 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 TimerSize Selects 16-bit or 32- bit counter operation 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TIMER2INTCLR Timer 2 Interrupt Clear Register 0x2C write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear TIMER2LOAD Timer 2 Load Register 0x20 read-write n 0x0 0xFFFFFFFF TIMER2MIS Timer 2 Mask Interrupt Status Register 0x34 read-only n 0x0 0xFFFFFFFF MIS Masked Timer Interrupt 0 1 TIMER2RIS Timer 2 Raw Interrupt Status Register 0x30 read-only n 0x0 0xFFFFFFFF RIS Raw Timer Interrupt 0 1 TIMER2VALUE Timer 2 Value Register 0x24 read-only n 0xFFFFFFFF 0xFFFFFFFF DUALTIMER_Secure Dual Timer (Secure) Timer 0x50002000 0x0 0x3C registers n TIMER1BGLOAD Timer 1 Background Load Register 0x18 read-write n 0x0 0xFFFFFFFF TIMER1CONTROL Timer 1 Control Register 0x8 read-write n 0x20 0xFFFFFFFF InterruptEnable Interrupt Enable bit 5 1 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 OneShotCount Selects one-shot or wrapping counter mode 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerEnable Timer Enable Enable bit 7 1 Disable Timer is disabled 0 Enable Timer is enabled 1 TimerMode Timer Mode bit 6 1 Free-Running Free-Running timer mode 0 Periodic Periodic timer mode 1 TimerPre Timer prescale bits 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 TimerSize Selects 16-bit or 32- bit counter operation 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TIMER1INTCLR Timer 1 Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear TIMER1LOAD Timer 1 Load Register 0x0 read-write n 0x0 0xFFFFFFFF TIMER1MIS Timer 1 Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Timer Interrupt 0 1 TIMER1RIS Timer 1 Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw Timer Interrupt 0 1 TIMER1VALUE Timer 1 Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF TIMER2BGLOAD Timer 2 Background Load Register 0x38 read-write n 0x0 0xFFFFFFFF TIMER2CONTROL Timer 2 Control Register 0x28 read-write n 0x20 0xFFFFFFFF InterruptEnable Interrupt Enable bit 5 1 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 OneShotCount Selects one-shot or wrapping counter mode 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerEnable Timer Enable Enable bit 7 1 Disable Timer is disabled 0 Enable Timer is enabled 1 TimerMode Timer Mode bit 6 1 Free-Running Free-Running timer mode 0 Periodic Periodic timer mode 1 TimerPre Timer prescale bits 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 TimerSize Selects 16-bit or 32- bit counter operation 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TIMER2INTCLR Timer 2 Interrupt Clear Register 0x2C write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear TIMER2LOAD Timer 2 Load Register 0x20 read-write n 0x0 0xFFFFFFFF TIMER2MIS Timer 2 Mask Interrupt Status Register 0x34 read-only n 0x0 0xFFFFFFFF MIS Masked Timer Interrupt 0 1 TIMER2RIS Timer 2 Raw Interrupt Status Register 0x30 read-only n 0x0 0xFFFFFFFF RIS Raw Timer Interrupt 0 1 TIMER2VALUE Timer 2 Value Register 0x24 read-only n 0xFFFFFFFF 0xFFFFFFFF GPIO0 General-purpose I/O 0 GPIO 0x40110000 0x0 0x3C registers n GPIO0 GPIO 0 combined 68 ALTFUNCCLR Alternate function clear Register 0x1C read-write n 0x0 0xFFFFFFFF ALTFUNCSET Alternate function set Register 0x18 read-write n 0x0 0xFFFFFFFF DATA Data Register 0x0 read-write n 0x0 0xFFFFFFFF DATAOUT Data Output Register 0x4 read-write n 0x0 0xFFFFFFFF INTCLEAR Interrupt CLEAR Register INTSTATUS 0x38 write-only n 0x0 0xFFFFFFFF oneToClear INTENCLR Interrupt enable clear Register 0x24 read-write n 0x0 0xFFFFFFFF INTENSET Interrupt enable set Register 0x20 read-write n 0x0 0xFFFFFFFF INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x34 read-write n 0x0 0xFFFFFFFF INTPOLSET Polarity-level, edge interrupt configuration set Register 0x30 read-write n 0x0 0xFFFFFFFF INTSTATUS Interrupt Status Register 0x38 read-only n 0x0 0xFFFFFFFF INTTYPECLR Interrupt type clear Register 0x2C read-write n 0x0 0xFFFFFFFF INTTYPESET Interrupt type set Register 0x28 read-write n 0x0 0xFFFFFFFF OUTENCLR Ouptut enable clear Register 0x14 read-write n 0x0 0xFFFFFFFF OUTENSET Ouptut enable set Register 0x10 read-write n 0x0 0xFFFFFFFF GPIO0_Secure General-purpose I/O 0 (Secure) GPIO 0x50110000 0x0 0x3C registers n ALTFUNCCLR Alternate function clear Register 0x1C read-write n 0x0 0xFFFFFFFF ALTFUNCSET Alternate function set Register 0x18 read-write n 0x0 0xFFFFFFFF DATA Data Register 0x0 read-write n 0x0 0xFFFFFFFF DATAOUT Data Output Register 0x4 read-write n 0x0 0xFFFFFFFF INTCLEAR Interrupt CLEAR Register INTSTATUS 0x38 write-only n 0x0 0xFFFFFFFF oneToClear INTENCLR Interrupt enable clear Register 0x24 read-write n 0x0 0xFFFFFFFF INTENSET Interrupt enable set Register 0x20 read-write n 0x0 0xFFFFFFFF INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x34 read-write n 0x0 0xFFFFFFFF INTPOLSET Polarity-level, edge interrupt configuration set Register 0x30 read-write n 0x0 0xFFFFFFFF INTSTATUS Interrupt Status Register 0x38 read-only n 0x0 0xFFFFFFFF INTTYPECLR Interrupt type clear Register 0x2C read-write n 0x0 0xFFFFFFFF INTTYPESET Interrupt type set Register 0x28 read-write n 0x0 0xFFFFFFFF OUTENCLR Ouptut enable clear Register 0x14 read-write n 0x0 0xFFFFFFFF OUTENSET Ouptut enable set Register 0x10 read-write n 0x0 0xFFFFFFFF GPTIMER General-Purpose Timer Timer 0x4010B000 0x0 0x20 registers n GPTIMER_COMP1 General-Purpose Timer (Comparator 1) 72 GPTALARM0 ALARM0 data value Register 0x10 read-write n 0x0 0xFFFFFFFF GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM1 ALARM1 data value Register 0x14 read-write n 0x0 0xFFFFFFFF GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTCOUNTER Counter data value Register 0x1C read-only n 0x0 0xFFFFFFFF GPTCOUNTER Current value of 32-bit Timer Counter 0 32 GPTINTC Interrupt clear Register 0x8 read-write n 0x0 0xFFFFFFFF GPTINTC Writing 0b1 disables the ALARM[n] Interrupt 0 2 GPTINTM Masked interrupt status Register 0x4 read-write n 0x0 0xFFFFFFFF GPTINTM Current masked status of the Interrupt 0 2 GPTINTR Raw interrupt status Register 0x18 read-only n 0x0 0xFFFFFFFF GPTINTR Raw interrupt state, before masking of GPTINTR Interrupt 0 3 GPTRESET Control Reset Register 0x0 read-only n 0x0 0xFFFFFFFF GPTRESET CPU0 interrupt status 0 2 GPTIMER_Secure General-Purpose Timer (Secure) Timer 0x5010B000 0x0 0x20 registers n GPTALARM0 ALARM0 data value Register 0x10 read-write n 0x0 0xFFFFFFFF GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM1 ALARM1 data value Register 0x14 read-write n 0x0 0xFFFFFFFF GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTCOUNTER Counter data value Register 0x1C read-only n 0x0 0xFFFFFFFF GPTCOUNTER Current value of 32-bit Timer Counter 0 32 GPTINTC Interrupt clear Register 0x8 read-write n 0x0 0xFFFFFFFF GPTINTC Writing 0b1 disables the ALARM[n] Interrupt 0 2 GPTINTM Masked interrupt status Register 0x4 read-write n 0x0 0xFFFFFFFF GPTINTM Current masked status of the Interrupt 0 2 GPTINTR Raw interrupt status Register 0x18 read-only n 0x0 0xFFFFFFFF GPTINTR Raw interrupt state, before masking of GPTINTR Interrupt 0 3 GPTRESET Control Reset Register 0x0 read-only n 0x0 0xFFFFFFFF GPTRESET CPU0 interrupt status 0 2 I2C0 I2C 0 I2C 0x40104000 0x0 0xFC registers n I2C_0 I2C0 Interrupt 34 AR Address Register 0x8 read-write n 0x0 0xFFFFFFFF ADD I2C Address 0 10 CR Control Register 0x0 read-write n 0x0 0xFFFFFFFF ACKEN Acknowledge Enable: Enable transmission of ACK when master-receiver 0 – acknowledge disabled, NACK transmitted, 1 – acknowledge enabled, ACK transmitted This bit must always be set if FIFO is implemented. 3 4 CLRFIFO Clear FIFO: initializes the FIFO to all zeros and clears the transfer size register 6 7 DIV_A Divisor A: Divisor for stage A clock divider. Divides the input pclk frequency by divisor_a + 1 8 14 DIV_B Divisor B: Divisor for stage B clock divider. Divides the output frequency from divisor_a by divisor_b + 1 14 16 HOLD Hold mode: Hold I2C sclk low until host services the data resources or clears this bit 1 - when no more data is available for transmit or no more data can be received, hold the sclk line low until serviced by the host. 0 - allow the transfer to terminate as soon as all the data has been transmitted or received. This bit has the same meaning in both master and slave modes. 4 5 MS Master/Slave: Overall interface mode 0 - slave, 1 - master 1 2 NEA Normal/Extended Address: 2 3 RW Read/Write: Direction of transfer 0 - master transmitter, 1 - master receiver This bit is used in master mode only. 0 1 SLVMON Slave Monitor mode: Slave monitor mode. 0 - normal operation, 1 - monitor mode 5 6 DR Data Register 0xC read-write n 0x0 0xFFFFFFFF DAT I2C Data 0 8 GFCR Glitch Filter Control Register 0x2C read-write n 0x0 0xFFFFFFFF GF Glitch Filter depth 0 4 IDR Interrupt Disable Register 0x28 write-only n 0x0 0xFFFFFFFF ARB_LOST Arbitration Lost 9 10 COMP Transfer Complete 0 1 DATA More Data 1 2 NACK Transfer Not Acknowledged 2 3 RX_OVF Receive Overflow 5 6 RX_UNF FIFO Receive Underflow 7 8 SLV_RDY Monitored Slave Ready 4 5 TO Transfer Time Out 3 4 TX_OVF FIFO Transmit Overflow 6 7 IER Interrupt Enable Register 0x24 write-only n 0x0 0xFFFFFFFF ARB_LOST Arbitration Lost 9 10 COMP Transfer Complete 0 1 DATA More Data 1 2 NACK Transfer Not Acknowledged 2 3 RX_OVF Receive Overflow 5 6 RX_UNF FIFO Receive Underflow 7 8 SLV_RDY Monitored Slave Ready 4 5 TO Transfer Time Out 3 4 TX_OVF FIFO Transmit Overflow 6 7 IMR Interrupt Mask Register 0x20 read-only n 0x2FF 0xFFFFFFFF ARB_LOST Arbitration Lost 9 10 COMP Transfer Complete 0 1 DATA More Data 1 2 NACK Transfer Not Acknowledged 2 3 RX_OVF Receive Overflow 5 6 RX_UNF FIFO Receive Underflow 7 8 SLV_RDY Monitored Slave Ready 4 5 TO Transfer Time Out 3 4 TX_OVF FIFO Transmit Overflow 6 7 ISR Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF ARB_LOST Arbitration Lost 9 10 COMP Transfer Complete 0 1 DATA More Data 1 2 NACK Transfer Not Acknowledged 2 3 RX_OVF Receive Overflow 5 6 RX_UNF FIFO Receive Underflow 7 8 SLV_RDY Monitored Slave Ready 4 5 TO Transfer Time Out 3 4 TX_OVF FIFO Transmit Overflow 6 7 SMPR Slave Monitor Pause Register 0x18 read-write n 0x0 0xFFFFFFFF PI Pause Interval 0 4 SR Status Register 0x4 read-only n 0x0 0xFFFFFFFF BA Bus Active: Indicates there is an ongoing transfer on the I2C bus. The I2C controller is not necessarily involved in it 8 9 RXDV Receiver Data Valid: Indicates that there is valid, new data to be read from the interface. 5 6 RXOVF Receiver Overflow: This flag is set when the receiver receives a byte of data before the previous byte has been read by the host. 7 8 RXRW RX read/write flag: Indicates the mode of the transmission received from a master. 3 4 TXDV Transmitter Data Valid: Indicates that there is still a byte of data to be transmitted by the interface. 6 7 TOR Time Out Register 0x1C read-write n 0x1F 0xFFFFFFFF TO Time Out 0 8 TSR Transfer Size Register 0x14 read-write n 0x0 0xFFFFFFFF TS Transfer Size 0 4 I2C0_Secure I2C 0 (Secure) I2C 0x50104000 0x0 0xFC registers n AR Address Register 0x8 read-write n 0x0 0xFFFFFFFF ADD I2C Address 0 10 CR Control Register 0x0 read-write n 0x0 0xFFFFFFFF ACKEN Acknowledge Enable: Enable transmission of ACK when master-receiver 0 – acknowledge disabled, NACK transmitted, 1 – acknowledge enabled, ACK transmitted This bit must always be set if FIFO is implemented. 3 4 CLRFIFO Clear FIFO: initializes the FIFO to all zeros and clears the transfer size register 6 7 DIV_A Divisor A: Divisor for stage A clock divider. Divides the input pclk frequency by divisor_a + 1 8 14 DIV_B Divisor B: Divisor for stage B clock divider. Divides the output frequency from divisor_a by divisor_b + 1 14 16 HOLD Hold mode: Hold I2C sclk low until host services the data resources or clears this bit 1 - when no more data is available for transmit or no more data can be received, hold the sclk line low until serviced by the host. 0 - allow the transfer to terminate as soon as all the data has been transmitted or received. This bit has the same meaning in both master and slave modes. 4 5 MS Master/Slave: Overall interface mode 0 - slave, 1 - master 1 2 NEA Normal/Extended Address: 2 3 RW Read/Write: Direction of transfer 0 - master transmitter, 1 - master receiver This bit is used in master mode only. 0 1 SLVMON Slave Monitor mode: Slave monitor mode. 0 - normal operation, 1 - monitor mode 5 6 DR Data Register 0xC read-write n 0x0 0xFFFFFFFF DAT I2C Data 0 8 GFCR Glitch Filter Control Register 0x2C read-write n 0x0 0xFFFFFFFF GF Glitch Filter depth 0 4 IDR Interrupt Disable Register 0x28 write-only n 0x0 0xFFFFFFFF ARB_LOST Arbitration Lost 9 10 COMP Transfer Complete 0 1 DATA More Data 1 2 NACK Transfer Not Acknowledged 2 3 RX_OVF Receive Overflow 5 6 RX_UNF FIFO Receive Underflow 7 8 SLV_RDY Monitored Slave Ready 4 5 TO Transfer Time Out 3 4 TX_OVF FIFO Transmit Overflow 6 7 IER Interrupt Enable Register 0x24 write-only n 0x0 0xFFFFFFFF ARB_LOST Arbitration Lost 9 10 COMP Transfer Complete 0 1 DATA More Data 1 2 NACK Transfer Not Acknowledged 2 3 RX_OVF Receive Overflow 5 6 RX_UNF FIFO Receive Underflow 7 8 SLV_RDY Monitored Slave Ready 4 5 TO Transfer Time Out 3 4 TX_OVF FIFO Transmit Overflow 6 7 IMR Interrupt Mask Register 0x20 read-only n 0x2FF 0xFFFFFFFF ARB_LOST Arbitration Lost 9 10 COMP Transfer Complete 0 1 DATA More Data 1 2 NACK Transfer Not Acknowledged 2 3 RX_OVF Receive Overflow 5 6 RX_UNF FIFO Receive Underflow 7 8 SLV_RDY Monitored Slave Ready 4 5 TO Transfer Time Out 3 4 TX_OVF FIFO Transmit Overflow 6 7 ISR Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF ARB_LOST Arbitration Lost 9 10 COMP Transfer Complete 0 1 DATA More Data 1 2 NACK Transfer Not Acknowledged 2 3 RX_OVF Receive Overflow 5 6 RX_UNF FIFO Receive Underflow 7 8 SLV_RDY Monitored Slave Ready 4 5 TO Transfer Time Out 3 4 TX_OVF FIFO Transmit Overflow 6 7 SMPR Slave Monitor Pause Register 0x18 read-write n 0x0 0xFFFFFFFF PI Pause Interval 0 4 SR Status Register 0x4 read-only n 0x0 0xFFFFFFFF BA Bus Active: Indicates there is an ongoing transfer on the I2C bus. The I2C controller is not necessarily involved in it 8 9 RXDV Receiver Data Valid: Indicates that there is valid, new data to be read from the interface. 5 6 RXOVF Receiver Overflow: This flag is set when the receiver receives a byte of data before the previous byte has been read by the host. 7 8 RXRW RX read/write flag: Indicates the mode of the transmission received from a master. 3 4 TXDV Transmitter Data Valid: Indicates that there is still a byte of data to be transmitted by the interface. 6 7 TOR Time Out Register 0x1C read-write n 0x1F 0xFFFFFFFF TO Time Out 0 8 TSR Transfer Size Register 0x14 read-write n 0x0 0xFFFFFFFF TS Transfer Size 0 4 I2C1 I2C 1 I2C 0x40105000 0x0 0xFC registers n I2C_1 I2C1 Interrupt 35 AR Address Register 0x8 read-write n 0x0 0xFFFFFFFF ADD I2C Address 0 10 CR Control Register 0x0 read-write n 0x0 0xFFFFFFFF ACKEN Acknowledge Enable: Enable transmission of ACK when master-receiver 0 – acknowledge disabled, NACK transmitted, 1 – acknowledge enabled, ACK transmitted This bit must always be set if FIFO is implemented. 3 4 CLRFIFO Clear FIFO: initializes the FIFO to all zeros and clears the transfer size register 6 7 DIV_A Divisor A: Divisor for stage A clock divider. Divides the input pclk frequency by divisor_a + 1 8 14 DIV_B Divisor B: Divisor for stage B clock divider. Divides the output frequency from divisor_a by divisor_b + 1 14 16 HOLD Hold mode: Hold I2C sclk low until host services the data resources or clears this bit 1 - when no more data is available for transmit or no more data can be received, hold the sclk line low until serviced by the host. 0 - allow the transfer to terminate as soon as all the data has been transmitted or received. This bit has the same meaning in both master and slave modes. 4 5 MS Master/Slave: Overall interface mode 0 - slave, 1 - master 1 2 NEA Normal/Extended Address: 2 3 RW Read/Write: Direction of transfer 0 - master transmitter, 1 - master receiver This bit is used in master mode only. 0 1 SLVMON Slave Monitor mode: Slave monitor mode. 0 - normal operation, 1 - monitor mode 5 6 DR Data Register 0xC read-write n 0x0 0xFFFFFFFF DAT I2C Data 0 8 GFCR Glitch Filter Control Register 0x2C read-write n 0x0 0xFFFFFFFF GF Glitch Filter depth 0 4 IDR Interrupt Disable Register 0x28 write-only n 0x0 0xFFFFFFFF ARB_LOST Arbitration Lost 9 10 COMP Transfer Complete 0 1 DATA More Data 1 2 NACK Transfer Not Acknowledged 2 3 RX_OVF Receive Overflow 5 6 RX_UNF FIFO Receive Underflow 7 8 SLV_RDY Monitored Slave Ready 4 5 TO Transfer Time Out 3 4 TX_OVF FIFO Transmit Overflow 6 7 IER Interrupt Enable Register 0x24 write-only n 0x0 0xFFFFFFFF ARB_LOST Arbitration Lost 9 10 COMP Transfer Complete 0 1 DATA More Data 1 2 NACK Transfer Not Acknowledged 2 3 RX_OVF Receive Overflow 5 6 RX_UNF FIFO Receive Underflow 7 8 SLV_RDY Monitored Slave Ready 4 5 TO Transfer Time Out 3 4 TX_OVF FIFO Transmit Overflow 6 7 IMR Interrupt Mask Register 0x20 read-only n 0x2FF 0xFFFFFFFF ARB_LOST Arbitration Lost 9 10 COMP Transfer Complete 0 1 DATA More Data 1 2 NACK Transfer Not Acknowledged 2 3 RX_OVF Receive Overflow 5 6 RX_UNF FIFO Receive Underflow 7 8 SLV_RDY Monitored Slave Ready 4 5 TO Transfer Time Out 3 4 TX_OVF FIFO Transmit Overflow 6 7 ISR Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF ARB_LOST Arbitration Lost 9 10 COMP Transfer Complete 0 1 DATA More Data 1 2 NACK Transfer Not Acknowledged 2 3 RX_OVF Receive Overflow 5 6 RX_UNF FIFO Receive Underflow 7 8 SLV_RDY Monitored Slave Ready 4 5 TO Transfer Time Out 3 4 TX_OVF FIFO Transmit Overflow 6 7 SMPR Slave Monitor Pause Register 0x18 read-write n 0x0 0xFFFFFFFF PI Pause Interval 0 4 SR Status Register 0x4 read-only n 0x0 0xFFFFFFFF BA Bus Active: Indicates there is an ongoing transfer on the I2C bus. The I2C controller is not necessarily involved in it 8 9 RXDV Receiver Data Valid: Indicates that there is valid, new data to be read from the interface. 5 6 RXOVF Receiver Overflow: This flag is set when the receiver receives a byte of data before the previous byte has been read by the host. 7 8 RXRW RX read/write flag: Indicates the mode of the transmission received from a master. 3 4 TXDV Transmitter Data Valid: Indicates that there is still a byte of data to be transmitted by the interface. 6 7 TOR Time Out Register 0x1C read-write n 0x1F 0xFFFFFFFF TO Time Out 0 8 TSR Transfer Size Register 0x14 read-write n 0x0 0xFFFFFFFF TS Transfer Size 0 4 I2C1_Secure I2C 1 (Secure) I2C 0x50105000 0x0 0xFC registers n AR Address Register 0x8 read-write n 0x0 0xFFFFFFFF ADD I2C Address 0 10 CR Control Register 0x0 read-write n 0x0 0xFFFFFFFF ACKEN Acknowledge Enable: Enable transmission of ACK when master-receiver 0 – acknowledge disabled, NACK transmitted, 1 – acknowledge enabled, ACK transmitted This bit must always be set if FIFO is implemented. 3 4 CLRFIFO Clear FIFO: initializes the FIFO to all zeros and clears the transfer size register 6 7 DIV_A Divisor A: Divisor for stage A clock divider. Divides the input pclk frequency by divisor_a + 1 8 14 DIV_B Divisor B: Divisor for stage B clock divider. Divides the output frequency from divisor_a by divisor_b + 1 14 16 HOLD Hold mode: Hold I2C sclk low until host services the data resources or clears this bit 1 - when no more data is available for transmit or no more data can be received, hold the sclk line low until serviced by the host. 0 - allow the transfer to terminate as soon as all the data has been transmitted or received. This bit has the same meaning in both master and slave modes. 4 5 MS Master/Slave: Overall interface mode 0 - slave, 1 - master 1 2 NEA Normal/Extended Address: 2 3 RW Read/Write: Direction of transfer 0 - master transmitter, 1 - master receiver This bit is used in master mode only. 0 1 SLVMON Slave Monitor mode: Slave monitor mode. 0 - normal operation, 1 - monitor mode 5 6 DR Data Register 0xC read-write n 0x0 0xFFFFFFFF DAT I2C Data 0 8 GFCR Glitch Filter Control Register 0x2C read-write n 0x0 0xFFFFFFFF GF Glitch Filter depth 0 4 IDR Interrupt Disable Register 0x28 write-only n 0x0 0xFFFFFFFF ARB_LOST Arbitration Lost 9 10 COMP Transfer Complete 0 1 DATA More Data 1 2 NACK Transfer Not Acknowledged 2 3 RX_OVF Receive Overflow 5 6 RX_UNF FIFO Receive Underflow 7 8 SLV_RDY Monitored Slave Ready 4 5 TO Transfer Time Out 3 4 TX_OVF FIFO Transmit Overflow 6 7 IER Interrupt Enable Register 0x24 write-only n 0x0 0xFFFFFFFF ARB_LOST Arbitration Lost 9 10 COMP Transfer Complete 0 1 DATA More Data 1 2 NACK Transfer Not Acknowledged 2 3 RX_OVF Receive Overflow 5 6 RX_UNF FIFO Receive Underflow 7 8 SLV_RDY Monitored Slave Ready 4 5 TO Transfer Time Out 3 4 TX_OVF FIFO Transmit Overflow 6 7 IMR Interrupt Mask Register 0x20 read-only n 0x2FF 0xFFFFFFFF ARB_LOST Arbitration Lost 9 10 COMP Transfer Complete 0 1 DATA More Data 1 2 NACK Transfer Not Acknowledged 2 3 RX_OVF Receive Overflow 5 6 RX_UNF FIFO Receive Underflow 7 8 SLV_RDY Monitored Slave Ready 4 5 TO Transfer Time Out 3 4 TX_OVF FIFO Transmit Overflow 6 7 ISR Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF ARB_LOST Arbitration Lost 9 10 COMP Transfer Complete 0 1 DATA More Data 1 2 NACK Transfer Not Acknowledged 2 3 RX_OVF Receive Overflow 5 6 RX_UNF FIFO Receive Underflow 7 8 SLV_RDY Monitored Slave Ready 4 5 TO Transfer Time Out 3 4 TX_OVF FIFO Transmit Overflow 6 7 SMPR Slave Monitor Pause Register 0x18 read-write n 0x0 0xFFFFFFFF PI Pause Interval 0 4 SR Status Register 0x4 read-only n 0x0 0xFFFFFFFF BA Bus Active: Indicates there is an ongoing transfer on the I2C bus. The I2C controller is not necessarily involved in it 8 9 RXDV Receiver Data Valid: Indicates that there is valid, new data to be read from the interface. 5 6 RXOVF Receiver Overflow: This flag is set when the receiver receives a byte of data before the previous byte has been read by the host. 7 8 RXRW RX read/write flag: Indicates the mode of the transmission received from a master. 3 4 TXDV Transmitter Data Valid: Indicates that there is still a byte of data to be transmitted by the interface. 6 7 TOR Time Out Register 0x1C read-write n 0x1F 0xFFFFFFFF TO Time Out 0 8 TSR Transfer Size Register 0x14 read-write n 0x0 0xFFFFFFFF TS Transfer Size 0 4 I2S0 I2S 0 I2S 0x40106000 0x0 0xFC registers n I2S_0 I2S0 Interrupt 36 CID_CTRL Clock Strobes and Interrupt Masks Control Register 0xC read-write n 0x0 0xFFFFFFFF CTRL Transceiver Control Register 0x0 read-write n 0x1900000 0xFFFFFFFF DEV_CONF Device Configuration Register 0x20 read-write n 0x208 0xFFFFFFFF INTR_STAT Interrupt Status Register 0x4 read-write n 0x3300 0xFFFFFFFF POLL_STAT Polling Status Register 0x24 read-write n 0x3 0xFFFFFFFF RFIFO_CTRL Receive FIFO Rhresholds Control Register 0x1C read-write n 0xF0000 0xFFFFFFFF RFIFO_STAT Receive FIFO Level Status Register 0x14 read-write n 0x0 0xFFFFFFFF SRR Sample Rate and Resolution Control Register 0x8 read-write n 0x0 0xFFFFFFFF TFIFO_CTRL Transmit FIFO Thresholds Control Register 0x18 read-write n 0xF0000 0xFFFFFFFF TFIFO_STAT Transmit FIFO Level Status Register 0x10 read-write n 0x0 0xFFFFFFFF I2S0_Secure I2S 0 (Secure) I2S 0x50106000 0x0 0xFC registers n CID_CTRL Clock Strobes and Interrupt Masks Control Register 0xC read-write n 0x0 0xFFFFFFFF CTRL Transceiver Control Register 0x0 read-write n 0x1900000 0xFFFFFFFF DEV_CONF Device Configuration Register 0x20 read-write n 0x208 0xFFFFFFFF INTR_STAT Interrupt Status Register 0x4 read-write n 0x3300 0xFFFFFFFF POLL_STAT Polling Status Register 0x24 read-write n 0x3 0xFFFFFFFF RFIFO_CTRL Receive FIFO Rhresholds Control Register 0x1C read-write n 0xF0000 0xFFFFFFFF RFIFO_STAT Receive FIFO Level Status Register 0x14 read-write n 0x0 0xFFFFFFFF SRR Sample Rate and Resolution Control Register 0x8 read-write n 0x0 0xFFFFFFFF TFIFO_CTRL Transmit FIFO Thresholds Control Register 0x18 read-write n 0xF0000 0xFFFFFFFF TFIFO_STAT Transmit FIFO Level Status Register 0x10 read-write n 0x0 0xFFFFFFFF NSPCTRL Non-secure Privilege Control Block NSPCTRL 0x40080000 0x0 0x1000 registers n AHBNSPPPC0 Non-Secure Unprivileged Access AHB slave Peripheral Protection Control #0 0x90 read-write n 0x0 0xFFFFFFFF AHBNSPPPCEXP0 Expansion 0 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA0 read-write n 0x0 0xFFFFFFFF AHBNSPPPCEXP1 Expansion 1 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA4 read-write n 0x0 0xFFFFFFFF AHBNSPPPCEXP2 Expansion 2 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA8 read-write n 0x0 0xFFFFFFFF AHBNSPPPCEXP3 Expansion 3 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xAC read-write n 0x0 0xFFFFFFFF APBNSPPPC0 Non-Secure Unprivileged Access APB slave Peripheral Protection Control 0 0xB0 read-write n 0x0 0xFFFFFFFF APBNSPPPC1 Non-Secure Unprivileged Access APB slave Peripheral Protection Control 1 0xB4 read-write n 0x0 0xFFFFFFFF APBNSPPPCEXP0 Expansion 0 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xC0 read-write n 0x0 0xFFFFFFFF APBNSPPPCEXP1 Expansion 1 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xC4 read-write n 0x0 0xFFFFFFFF APBNSPPPCEXP2 Expansion 2 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xC8 read-write n 0x0 0xFFFFFFFF APBNSPPPCEXP3 Expansion 3 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xCC read-write n 0x0 0xFFFFFFFF QSPIFCTRL QSPI Flash Controller QSPI 0x4010A000 0x0 0xB0 registers n QSPI QSPI Interrupt 38 DEVREADINSTR Device Read Instruction Register 0x4 read-write n 0x3 0xFFFFFFFF ADDRTRTYPESSPI Address Transfer Type for Standard SPI modes 12 14 DATATRTYPESSPI Data Transfer Type for Standard SPI modes 16 18 DDRBITEN DDR Bit Enable 10 11 INSTRTYPE Instruction Type 8 10 MODEBITEN Mode Bit Enable 20 21 READDUMCLKCYCNUM Number of Dummy Clock Cycles required by device for Read Instruction 24 29 ROPCODE Read Opcode to use when not in XIP mode 0 8 DEVSIZE Device Size Configuration Register 0x14 read-write n 0x101002 0xFFFFFFFF ADDRBYTENUM Number of address bytes 0 4 BYTEPERBLKNUM Number of bytes per block 16 21 BYTEPERDEVPGNUM Number of bytes per device page 4 16 FDEVSIZECS0 Size of Flash Device connected to CS[0] pin 21 23 FDEVSIZECS1 Size of Flash Device connected to CS[1] pin 23 25 FDEVSIZECS2 Size of Flash Device connected to CS[2] pin 25 27 FDEVSIZECS3 Size of Flash Device connected to CS[3] pin 27 29 DEVWRITEINSTR Device Write Instruction Configuration Register 0x8 read-write n 0x2 0xFFFFFFFF ADDRTRTYPESSPI Address Transfer Type for Standard SPI modes 12 14 DATATRTYPESSPI Data Transfer Type for Standard SPI modes 16 18 WELDISABLE WEL Disable 8 9 WRITEDUMCLKCYCNUM Number of Dummy Clock Cycles required by device for Write Instruction 24 29 WROPCODE Write Opcode 0 8 FLASHCMDADDR Flash Command Address Register 0x94 read-write n 0x0 0xFFFFFFFF FLASHCMDCTRL Flash Command Control Register 0x90 read-write n 0x0 0xFFFFFFFF ADDRBYTENUM Number of Address Bytes 16 18 CMDADDREN Command Address Enable 19 20 CMDEXEC Execute the command 0 1 CMDEXINPROG Command execution in progress 1 2 CMDOPCODE Command Opcode 24 32 DUMCYCNUM Number of Dummy Cycles 7 12 MODEBITEN Mode Bit Enable 18 19 RDATABYTENUM Number of Read Data Bytes 20 23 RDATAEN Read Data Enable 23 24 WRDATABYTENUM Number of Write Data Bytes 12 15 WRDATAEN Write Data Enable 15 16 FLASHCMDRDATALOW Flash Command Read Data Register (Lower) 0xA0 read-only n 0x0 0xFFFFFFFF FLASHCMDRDATAUP Flash Command Read Data Register (Upper) 0xA4 read-only n 0x0 0xFFFFFFFF FLASHCMDWRDATALOW Flash Command Write Data Register (Lower) 0xA8 read-write n 0x0 0xFFFFFFFF FLASHCMDWRDATAUP Flash Command Write Data Register (Upper) 0xAC read-write n 0x0 0xFFFFFFFF QSPICFG QSPI Configuration Register 0x0 read-write n 0x80780081 0xFFFFFFFF AHBDECEN Enable AHB Decoder 23 24 CLKPHASE Clock phase, this maps to the standard SPI CPHA transfer format 2 3 CLKPOLARITY Clock polarity outside SPI word. This maps to the standard SPI CPOL transfer format 1 2 DTREN Enable DTR Protocol 24 25 ENAHBADDRRM Enable AHB Address Re-mapping 16 17 ENDIRACCCTR Enable Direct Access Controller 7 8 ENDMAPIF Enable DMA Peripheral Interface 15 16 ENTRXIPMODEIMM Enter XIP Mode immediately 18 19 ENTRXIPMODEONR Enter XIP Mode on next READ 17 18 LEGIPMODEEN Legacy IP Mode Enable 8 9 MAMOBRDIV Master mode baud rate divisor (2 to 32) 19 23 PERCSLINES Peripheral chip select lines 10 14 ss3 n_ss_out: 0b0111 0b0111 ssinactive n_ss_out: 0b1111 (no peripheral selected) 0b1111 ss2 n_ss_out: 0b1011 0bx011 ss1 n_ss_out: 0b1101 0bxx01 ss0 n_ss_out: 0b1110 0bxxx0 PERSELDEC Peripheral select decode 9 10 Disabled Only 1 of 4 selects n_ss_out is active 0 Enabled Allow external 4-to-16 decode 1 PHYMODEEN PHY Mode enable 3 4 PIPLIDLE Serial Interface and QSPI pipeline is IDLE 31 32 PIPLPHYEN Pipeline PHY Mode enable 25 26 QSPIEN QSPI Enable 0 1 WPPINDRV Set to drive the WP pin of Flash device 14 15 REMAPADDR Remap Address Register 0x24 read-write n 0x0 0xFFFFFFFF QSPIFCTRL_Secure QSPI Flash Controller (Secure) QSPI 0x5010A000 0x0 0xB0 registers n DEVREADINSTR Device Read Instruction Register 0x4 read-write n 0x3 0xFFFFFFFF ADDRTRTYPESSPI Address Transfer Type for Standard SPI modes 12 14 DATATRTYPESSPI Data Transfer Type for Standard SPI modes 16 18 DDRBITEN DDR Bit Enable 10 11 INSTRTYPE Instruction Type 8 10 MODEBITEN Mode Bit Enable 20 21 READDUMCLKCYCNUM Number of Dummy Clock Cycles required by device for Read Instruction 24 29 ROPCODE Read Opcode to use when not in XIP mode 0 8 DEVSIZE Device Size Configuration Register 0x14 read-write n 0x101002 0xFFFFFFFF ADDRBYTENUM Number of address bytes 0 4 BYTEPERBLKNUM Number of bytes per block 16 21 BYTEPERDEVPGNUM Number of bytes per device page 4 16 FDEVSIZECS0 Size of Flash Device connected to CS[0] pin 21 23 FDEVSIZECS1 Size of Flash Device connected to CS[1] pin 23 25 FDEVSIZECS2 Size of Flash Device connected to CS[2] pin 25 27 FDEVSIZECS3 Size of Flash Device connected to CS[3] pin 27 29 DEVWRITEINSTR Device Write Instruction Configuration Register 0x8 read-write n 0x2 0xFFFFFFFF ADDRTRTYPESSPI Address Transfer Type for Standard SPI modes 12 14 DATATRTYPESSPI Data Transfer Type for Standard SPI modes 16 18 WELDISABLE WEL Disable 8 9 WRITEDUMCLKCYCNUM Number of Dummy Clock Cycles required by device for Write Instruction 24 29 WROPCODE Write Opcode 0 8 FLASHCMDADDR Flash Command Address Register 0x94 read-write n 0x0 0xFFFFFFFF FLASHCMDCTRL Flash Command Control Register 0x90 read-write n 0x0 0xFFFFFFFF ADDRBYTENUM Number of Address Bytes 16 18 CMDADDREN Command Address Enable 19 20 CMDEXEC Execute the command 0 1 CMDEXINPROG Command execution in progress 1 2 CMDOPCODE Command Opcode 24 32 DUMCYCNUM Number of Dummy Cycles 7 12 MODEBITEN Mode Bit Enable 18 19 RDATABYTENUM Number of Read Data Bytes 20 23 RDATAEN Read Data Enable 23 24 WRDATABYTENUM Number of Write Data Bytes 12 15 WRDATAEN Write Data Enable 15 16 FLASHCMDRDATALOW Flash Command Read Data Register (Lower) 0xA0 read-only n 0x0 0xFFFFFFFF FLASHCMDRDATAUP Flash Command Read Data Register (Upper) 0xA4 read-only n 0x0 0xFFFFFFFF FLASHCMDWRDATALOW Flash Command Write Data Register (Lower) 0xA8 read-write n 0x0 0xFFFFFFFF FLASHCMDWRDATAUP Flash Command Write Data Register (Upper) 0xAC read-write n 0x0 0xFFFFFFFF QSPICFG QSPI Configuration Register 0x0 read-write n 0x80780081 0xFFFFFFFF AHBDECEN Enable AHB Decoder 23 24 CLKPHASE Clock phase, this maps to the standard SPI CPHA transfer format 2 3 CLKPOLARITY Clock polarity outside SPI word. This maps to the standard SPI CPOL transfer format 1 2 DTREN Enable DTR Protocol 24 25 ENAHBADDRRM Enable AHB Address Re-mapping 16 17 ENDIRACCCTR Enable Direct Access Controller 7 8 ENDMAPIF Enable DMA Peripheral Interface 15 16 ENTRXIPMODEIMM Enter XIP Mode immediately 18 19 ENTRXIPMODEONR Enter XIP Mode on next READ 17 18 LEGIPMODEEN Legacy IP Mode Enable 8 9 MAMOBRDIV Master mode baud rate divisor (2 to 32) 19 23 PERCSLINES Peripheral chip select lines 10 14 ss3 n_ss_out: 0b0111 0b0111 ssinactive n_ss_out: 0b1111 (no peripheral selected) 0b1111 ss2 n_ss_out: 0b1011 0bx011 ss1 n_ss_out: 0b1101 0bxx01 ss0 n_ss_out: 0b1110 0bxxx0 PERSELDEC Peripheral select decode 9 10 Disabled Only 1 of 4 selects n_ss_out is active 0 Enabled Allow external 4-to-16 decode 1 PHYMODEEN PHY Mode enable 3 4 PIPLIDLE Serial Interface and QSPI pipeline is IDLE 31 32 PIPLPHYEN Pipeline PHY Mode enable 25 26 QSPIEN QSPI Enable 0 1 WPPINDRV Set to drive the WP pin of Flash device 14 15 REMAPADDR Remap Address Register 0x24 read-write n 0x0 0xFFFFFFFF QSPI_MPC QSPI Flash Memory Protection Controller MPC 0x50120000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index Register 0x10 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 32 bit[3_0] Block size 0 4 CTRL MPC Control Register 0x0 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 32 bit[4] Security error response configuration 4 5 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 7 bit[7] Data interface gating acknowledge (RO) 7 8 bit[8] Auto-increment 8 9 INT_CLEAR Interrupt clear 0x24 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 17 bit[17] cfg_ns 17 18 INT_SET Interrupt set. Debug purpose only 0x34 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 S32KTIMER S32K Timer Timer 0x4002F000 0x0 0x10 registers n S32KTIMER Timer 1 2 CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 EXTCLK External Clock Enable 2 3 EXTIN External Input as Enable 1 2 INTEN Interrupt Enable 3 4 INTCLEAR Timer Interrupt clear Register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF oneToClear INTSTATUS Timer Interrupt status Register 0xC read-only n 0x0 0xFFFFFFFF RELOAD Counter Reload Value 0x8 read-write n 0x0 0xFFFFFFFF VALUE Current Timer Counter Value 0x4 read-write n 0x0 0xFFFFFFFF S32KTIMER_Secure S32K Timer (Secure) IO 0x5002F000 0x0 0x400 registers n ALI_ACK0 Analog Input Acknowledge Register 0 (P0/P1/P2/P3) 0x18 read-write n 0x0 0xFFFFFFFF ali_ack_p0 Analog In Mode Acknowledge: P0[7:0] 0 8 read-only ali_ack_p1 Analog In Mode Acknowledge: P1[7:0] 8 16 read-only ali_ack_p2 Analog In Mode Acknowledge: P2[7:0] 16 24 read-only ali_ack_p3 Analog In Mode Acknowledge: P3[7:0] 24 32 read-only ALI_ACK1 Analog Input Acknowledge Register 1 (P4/P5/P6) 0x1C read-write n 0x0 0xFFFFFFFF ali_ack_p4 Analog In Mode Acknowledge: P4[7:0] 0 8 read-only ali_ack_p5 Analog In Mode Acknowledge: P5[7:0] 8 16 read-only ali_ack_p6 Analog In Mode Acknowledge: P6[0] 16 17 read-only ALI_CONNECT0 Analog I/O Connection Control Register 0 0x20 read-write n 0x0 0xFFFFFFFF ALI_CONNECT1 Analog I/O Connection Control Register 1 0x24 read-write n 0x0 0xFFFFFFFF ALI_REQ0 Analog Input Request Register 0 (P0/P1/P2/P3) 0x10 read-write n 0x0 0xFFFFFFFF ali_req_p0 Analog Input Mode Request: P0[7:0] 0 8 read-write ali_req_p1 Analog Input Mode Request: P1[7:0] 8 16 read-write ali_req_p2 Analog Input Mode Request: P2[7:0] 16 24 read-write ali_req_p3 Analog Input Mode Request: P3[7:0] 24 32 read-write ALI_REQ1 Analog Input Request Register 1 (P4/P5/P6) 0x14 read-write n 0x0 0xFFFFFFFF ali_req_p4 Analog Input Mode Request: P4[7:0] 0 8 read-write ali_req_p5 Analog Input Mode Request: P5[7:0] 8 16 read-write ali_req_p6 Analog Input Mode Request: P6[0] 16 17 read-write I2CM0_ACK I2C Master 0 I/O Acknowledge 0x54 read-write n 0x0 0xFFFFFFFF mapping_ack I2C Master 0 I/O Acknowledge 4 5 read-only I2CM0_REQ I2C Master 0 I/O Request 0x50 read-write n 0x0 0xFFFFFFFF mapping_req I2C Master 0 I/O Request 4 5 read-write I2CM1_ACK I2C Master 1 I/O Acknowledge 0x5C read-write n 0x0 0xFFFFFFFF mapping_ack I2C Master 1 I/O Acknowledge 4 5 read-only I2CM1_REQ I2C Master 1 I/O Request 0x58 read-write n 0x0 0xFFFFFFFF mapping_req I2C Master 1 I/O Request 4 5 read-write I2CM2_ACK I2C Master 2 I/O Acknowledge 0x64 read-write n 0x0 0xFFFFFFFF mapping_ack I2C Master 2 I/O Acknowledge 4 5 read-only I2CM2_REQ I2C Master 2 I/O Request 0x60 read-write n 0x0 0xFFFFFFFF mapping_req I2C Master 2 I/O Request 4 5 read-write I2CS_ACK I2C Slave I/O Acknowledge 0x6C read-write n 0x0 0xFFFFFFFF io_sel I2C Slave I/O Mapping Acknowledge 0 2 read-only mapping_ack I2C Slave I/O Acknowledge 4 5 read-only I2CS_REQ I2C Slave I/O Request 0x68 read-write n 0x0 0xFFFFFFFF io_sel I2C Slave I/O Mapping Select 0 2 read-write mapping_req I2C Slave I/O Request 4 5 read-write OWM_ACK 1-Wire Master I/O Mode Acknowledge 0x94 read-write n 0x0 0xFFFFFFFF epu_io_ack External Pullup Control Line I/O Acknowledge 5 6 read-write mapping_ack 1-Wire Line I/O Acknowledge 4 5 read-write OWM_REQ 1-Wire Master I/O Mode Request 0x90 read-write n 0x0 0xFFFFFFFF epu_io_req External Pullup Control Line I/O Request 5 6 read-write mapping_req 1-Wire Line I/O Request 4 5 read-write SPI0_ACK SPI Master 0 I/O Mode Acknowledge 0x74 read-write n 0x0 0xFFFFFFFF core_io_ack SPI Master 0 Core I/O Acknowledge 4 5 read-only fast_mode SPI Master 0 Fast Mode Acknowledge 24 25 read-only quad_io_ack SPI Master 0 Quad I/O Acknowledge 20 21 read-only ss0_io_ack SPI Master 0 SS[0] I/O Acknowledge 8 9 read-only ss1_io_ack SPI Master 0 SS[1] I/O Acknowledge 9 10 read-only ss2_io_ack SPI Master 0 SS[2] I/O Acknowledge 10 11 read-only ss3_io_ack SPI Master 0 SS[3] I/O Acknowledge 11 12 read-only ss4_io_ack SPI Master 0 SS[4] I/O Acknowledge 12 13 read-only SPI0_REQ SPI Master 0 I/O Mode Request 0x70 read-write n 0x0 0xFFFFFFFF core_io_req SPI Master 0 Core I/O Request 4 5 read-write fast_mode SPI Master 0 Fast Mode Request 24 25 read-write quad_io_req SPI Master 0 Quad I/O Request 20 21 read-write ss0_io_req SPI Master 0 SS[0] I/O Request 8 9 read-write ss1_io_req SPI Master 0 SS[1] I/O Request 9 10 read-write ss2_io_req SPI Master 0 SS[2] I/O Request 10 11 read-write ss3_io_req SPI Master 0 SS[3] I/O Request 11 12 read-write ss4_io_req SPI Master 0 SS[4] I/O Request 12 13 read-write SPI1_ACK SPI Master 1 I/O Mode Acknowledge 0x7C read-write n 0x0 0xFFFFFFFF core_io_ack SPI Master 1 Core I/O Acknowledge 4 5 read-only fast_mode SPI Master 1 Fast Mode Acknowledge 24 25 read-only quad_io_ack SPI Master 1 Quad I/O Acknowledge 20 21 read-only ss0_io_ack SPI Master 1 SS[0] I/O Acknowledge 8 9 read-only ss1_io_ack SPI Master 1 SS[1] I/O Acknowledge 9 10 read-only ss2_io_ack SPI Master 1 SS[2] I/O Acknowledge 10 11 read-only SPI1_REQ SPI Master 1 I/O Mode Request 0x78 read-write n 0x0 0xFFFFFFFF core_io_req SPI Master 1 Core I/O Request 4 5 read-write fast_mode SPI Master 1 Fast Mode Request 24 25 read-write quad_io_req SPI Master 1 Quad I/O Request 20 21 read-write ss0_io_req SPI Master 1 SS[0] I/O Request 8 9 read-write ss1_io_req SPI Master 1 SS[1] I/O Request 9 10 read-write ss2_io_req SPI Master 1 SS[2] I/O Request 10 11 read-write SPI2_ACK SPI Master 2 I/O Mode Acknowledge 0x84 read-write n 0x0 0xFFFFFFFF core_io_ack SPI Master 2 Core I/O Acknowledge 4 5 read-only fast_mode SPI Master 2 Fast Mode Acknowledge 24 25 read-only mapping_ack SPI Master 2 I/O Mapping Acknowledge 0 1 read-only quad_io_ack SPI Master 2 Quad I/O Acknowledge 20 21 read-only sr0_io_req SPI Master 2 SR[0] I/O Acknowledge 16 17 read-only sr1_io_req SPI Master 2 SR[1] I/O Acknowledge 17 18 read-only ss0_io_ack SPI Master 2 SS[0] I/O Acknowledge 8 9 read-only ss1_io_ack SPI Master 2 SS[1] I/O Acknowledge 9 10 read-only ss2_io_ack SPI Master 2 SS[2] I/O Acknowledge 10 11 read-only SPI2_REQ SPI Master 2 I/O Mode Request 0x80 read-write n 0x0 0xFFFFFFFF core_io_req SPI Master 2 Core I/O Request 4 5 read-write fast_mode SPI Master 2 Fast Mode Request 24 25 read-write mapping_req SPI Master 2 I/O Mapping Select 0 1 read-write quad_io_req SPI Master 2 Quad I/O Request 20 21 read-write sr0_io_req SPI Master 2 SR[0] I/O Request 16 17 read-write sr1_io_req SPI Master 2 SR[1] I/O Request 17 18 read-write ss0_io_req SPI Master 2 SS[0] I/O Request 8 9 read-write ss1_io_req SPI Master 2 SS[1] I/O Request 9 10 read-write ss2_io_req SPI Master 2 SS[2] I/O Request 10 11 read-write SPIB_ACK SPI Bridge I/O Mode Acknowledge 0x8C read-write n 0x0 0xFFFFFFFF core_io_ack SPI Bridge Core I/O Acknowledge 4 5 read-only fast_mode SPI Bridge Fast Mode Acknowledge 12 13 read-only quad_io_ack SPI Bridge Quad I/O Acknowledge 8 9 read-only SPIB_REQ SPI Bridge I/O Mode Request 0x88 read-write n 0x0 0xFFFFFFFF core_io_req SPI Bridge Core I/O Request 4 5 read-only fast_mode SPI Bridge Fast Mode Request 12 13 read-only quad_io_req SPI Bridge Quad I/O Request 8 9 read-only SPIX_ACK SPIX I/O Mode Acknowledge 0x2C read-write n 0x0 0xFFFFFFFF core_io_ack SPIX Core I/O Acknowledge 4 5 read-only fast_mode SPIX Fast Mode Acknowledge 16 17 read-only quad_io_ack SPIX Quad I/O Acknowledge 12 13 read-only ss0_io_ack SPIX SS[0] I/O Acknowledge 8 9 read-only ss1_io_ack SPIX SS[1] I/O Acknowledge 9 10 read-only ss2_io_ack SPIX SS[2] I/O Acknowledge 10 11 read-only SPIX_REQ SPIX I/O Mode Request 0x28 read-write n 0x0 0xFFFFFFFF core_io_req SPIX Core I/O Request 4 5 read-write fast_mode SPIX Fast Mode Request 16 17 read-write quad_io_req SPIX Quad I/O Request 12 13 read-write ss0_io_req SPIX SS[0] I/O Request 8 9 read-write ss1_io_req SPIX SS[1] I/O Request 9 10 read-write ss2_io_req SPIX SS[2] I/O Request 10 11 read-write UART0_ACK UART0 I/O Mode Acknowledge 0x34 read-write n 0x0 0xFFFFFFFF cts_io_req UART0 CTS I/O Acknowledge 5 6 read-only cts_map UART0 CTS I/O Mapping Acknowledge 1 2 read-only io_map UART0 TX/RX I/O Mapping Acknowledge 0 1 read-only io_req UART0 TX/RX I/O Acknowledge 4 5 read-only rts_io_req UART0 RTS I/O Acknowledge 6 7 read-only rts_map UART0 RTS I/O Mapping Acknowledge 2 3 read-only UART0_REQ UART0 I/O Mode Request 0x30 read-write n 0x0 0xFFFFFFFF cts_io_req UART0 CTS I/O Request 5 6 read-write cts_map UART0 CTS I/O Mapping Select 1 2 read-write io_map UART0 TX/RX I/O Mapping Select 0 1 read-write io_req UART0 TX/RX I/O Request 4 5 read-write rts_io_req UART0 RTS I/O Request 6 7 read-write rts_map UART0 RTS I/O Mapping Select 2 3 read-write UART1_ACK UART1 I/O Mode Acknowledge 0x3C read-write n 0x0 0xFFFFFFFF cts_io_req UART1 CTS I/O Acknowledge 5 6 read-only cts_map UART1 CTS I/O Mapping Acknowledge 1 2 read-only io_map UART1 TX/RX I/O Mapping Acknowledge 0 1 read-only io_req UART1 TX/RX I/O Acknowledge 4 5 read-only rts_io_req UART1 RTS I/O Acknowledge 6 7 read-only rts_map UART1 RTS I/O Mapping Acknowledge 2 3 read-only UART1_REQ UART1 I/O Mode Request 0x38 read-write n 0x0 0xFFFFFFFF cts_io_req UART1 CTS I/O Request 5 6 read-write cts_map UART1 CTS I/O Mapping Select 1 2 read-write io_map UART1 TX/RX I/O Mapping Select 0 1 read-write io_req UART1 TX/RX I/O Request 4 5 read-write rts_io_req UART1 RTS I/O Request 6 7 read-write rts_map UART1 RTS I/O Mapping Select 2 3 read-write UART2_ACK UART2 I/O Mode Acknowledge 0x44 read-write n 0x0 0xFFFFFFFF cts_io_req UART2 CTS I/O Acknowledge 5 6 read-only cts_map UART2 CTS I/O Mapping Acknowledge 1 2 read-only io_map UART2 TX/RX I/O Mapping Acknowledge 0 1 read-only io_req UART2 TX/RX I/O Acknowledge 4 5 read-only rts_io_req UART2 RTS I/O Acknowledge 6 7 read-only rts_map UART2 RTS I/O Mapping Acknowledge 2 3 read-only UART2_REQ UART2 I/O Mode Request 0x40 read-write n 0x0 0xFFFFFFFF cts_io_req UART2 CTS I/O Request 5 6 read-write cts_map UART2 CTS I/O Mapping Select 1 2 read-write io_map UART2 TX/RX I/O Mapping Select 0 1 read-write io_req UART2 TX/RX I/O Request 4 5 read-write rts_io_req UART2 RTS I/O Request 6 7 read-write rts_map UART2 RTS I/O Mapping Select 2 3 read-write UART3_ACK UART3 I/O Mode Acknowledge 0x4C read-write n 0x0 0xFFFFFFFF cts_io_req UART3 CTS I/O Acknowledge 5 6 read-only cts_map UART3 CTS I/O Mapping Acknowledge 1 2 read-only io_map UART3 TX/RX I/O Mapping Acknowledge 0 1 read-only io_req UART3 TX/RX I/O Acknowledge 4 5 read-only rts_io_req UART3 RTS I/O Acknowledge 6 7 read-only rts_map UART3 RTS I/O Mapping Acknowledge 2 3 read-only UART3_REQ UART3 I/O Mode Request 0x48 read-write n 0x0 0xFFFFFFFF cts_io_req UART3 CTS I/O Request 5 6 read-write cts_map UART3 CTS I/O Mapping Select 1 2 read-write io_map UART3 TX/RX I/O Mapping Select 0 1 read-write io_req UART3 TX/RX I/O Request 4 5 read-write rts_io_req UART3 RTS I/O Request 6 7 read-write rts_map UART3 RTS I/O Mapping Select 2 3 read-write WUD_ACK0 Wakeup Detect Mode Acknowledge Register 0 (P0/P1/P2/P3) 0x8 read-write n 0x0 0xFFFFFFFF wud_ack_p0 WUD Mode Acknowledge: P0[7:0] 0 8 read-only wud_ack_p1 WUD Mode Acknowledge: P1[7:0] 8 16 read-only wud_ack_p2 WUD Mode Acknowledge: P2[7:0] 16 24 read-only wud_ack_p3 WUD Mode Acknowledge: P3[7:0] 24 32 read-only WUD_ACK1 Wakeup Detect Mode Acknowledge Register 1 (P4/P5/P6) 0xC read-write n 0x0 0xFFFFFFFF wud_ack_p4 WUD Mode Acknowledge: P4[7:0] 0 8 read-only wud_ack_p5 WUD Mode Acknowledge: P5[7:0] 8 16 read-only wud_ack_p6 WUD Mode Acknowledge: P6[7:0] 16 17 read-only WUD_REQ0 Wakeup Detect Mode Request Register 0 (P0/P1/P2/P3) 0x0 read-write n 0x0 0xFFFFFFFF wud_req_p0 Wakeup Detect Request Mode: P0[7:0] 0 8 read-write wud_req_p1 Wakeup Detect Request Mode: P1[7:0] 8 16 read-write wud_req_p2 Wakeup Detect Request Mode: P2[7:0] 16 24 read-write wud_req_p3 Wakeup Detect Request Mode: P3[7:0] 24 32 read-write WUD_REQ1 Wakeup Detect Mode Request Register 1 (P4/P5/P6) 0x4 read-write n 0x0 0xFFFFFFFF wud_req_p4 Wakeup Detect Request Mode: P4[7:0] 0 8 read-write wud_req_p5 Wakeup Detect Request Mode: P5[7:0] 8 16 read-write wud_req_p6 Wakeup Detect Request Mode: P6[0] 16 17 read-write S32KWATCHDOG S32K Watchdog Watchdog 0x4002E000 0x0 0xC04 registers n WDOGCONTROL Watchdog Control Register 0x8 read-write n 0x0 0xFFFFFFFF INTEN Enable the interrupt event 0 1 Disable Disable Watchdog Interrupt 0 Enable Enable Watchdog interrupt 1 RESEN Enable watchdog reset output 1 2 Disable Disable Watchdog reset 0 Enable Enable Watchdog reset 1 WDOGINTCLR Watchdog Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear WDOGLOAD Watchdog Load Register 0x0 read-write n 0xFFFFFFFF 0xFFFFFFFF WDOGLOCK Watchdog Lock Register 0xC00 read-write n 0x0 0xFFFFFFFF Access Enable register writes 1 32 Status Register write enable status 0 1 Enabled Write access to all other registers is enabled. This is the default 0 Disabled Write access to all other registers is disabled 1 WDOGMIS Watchdog Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Watchdog Interrupt 0 1 WDOGRIS Watchdog Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw watchdog Interrupt 0 1 WDOGVALUE Watchdog Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF S32KWATCHDOG_Secure S32K Watchdog (Secure) Watchdog 0x5002E000 0x0 0xC04 registers n WDOGCONTROL Watchdog Control Register 0x8 read-write n 0x0 0xFFFFFFFF INTEN Enable the interrupt event 0 1 Disable Disable Watchdog Interrupt 0 Enable Enable Watchdog interrupt 1 RESEN Enable watchdog reset output 1 2 Disable Disable Watchdog reset 0 Enable Enable Watchdog reset 1 WDOGINTCLR Watchdog Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear WDOGLOAD Watchdog Load Register 0x0 read-write n 0xFFFFFFFF 0xFFFFFFFF WDOGLOCK Watchdog Lock Register 0xC00 read-write n 0x0 0xFFFFFFFF Access Enable register writes 1 32 Status Register write enable status 0 1 Enabled Write access to all other registers is enabled. This is the default 0 Disabled Write access to all other registers is disabled 1 WDOGMIS Watchdog Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Watchdog Interrupt 0 1 WDOGRIS Watchdog Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw watchdog Interrupt 0 1 WDOGVALUE Watchdog Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF SAU Security Attribution Unit SAU 0xE000EDD0 0x0 0x20 registers n CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ALLNS Security attribution if SAU disabled 1 2 Secure Memory is marked as secure 0 Non_Secure Memory is marked as non-secure 1 ENABLE Enable 0 1 Disable SAU is disabled 0 Enable SAU is enabled 1 RBAR Region Base Address Register 0xC read-write n 0x0 0xFFFFFFFF BADDR Base Address 5 32 RLAR Region Limit Address Register 0x10 read-write n 0x0 0xFFFFFFFF ENABLE SAU Region enabled 0 1 LADDR Limit Address 5 32 NSC Non-Secure Callable 1 2 RNR Region Number Register 0x8 read-write n 0x0 0xFFFFFFFF REGION Currently selected SAU region 0 8 SFSR Secure Fault Status Register 0x14 read-write n 0x0 0xFFFFFFFF AUVIOL Attribution unit violation flag 3 4 INVEP Invalid entry pointd 0 1 INVER Invalid exception return flag 2 3 INVIS Invalid integrity signature flag 1 2 INVTRAN Invalid transition flag 4 5 LSERR Lazy state error flag 7 8 LSPERR Lazy state preservation error flag 5 6 SFARVALID Secure fault address valid 6 7 TYPE Type Register 0x4 read-only n 0x0 0xFFFFFFFF SREGION Number of implemented SAU regions 0 8 SCC Serial Communication Controller SCC 0x4010C800 0x0 0x1000 registers n AZ_CTRL AZ Control Register 0x200 read-write n 0x0 0xFFFFFFFF SCC_nPORESETAON_nPORESET_SEL Memory subsystem reset select: 1: nPORESETAON 0: NPORESET 9 10 BBGEN_CTRL Body Bias Enable Control Register 0x220 read-write n 0x0 0xFFFFFFFF CASTOR_OTP_CTRL OTP Control Register 0x204 read-write n 0x0 0xFFFFFFFF pad_sel OTP control selection 30 31 scc_addr otp addr from scc 0 16 scc_din din from scc 16 17 scc_otp_ctrl scc otp control 20 30 scc_readen readen from scc 18 19 scc_sel OTP control selection 31 32 scc_web web from scc 17 18 CHIP_ID Chip ID Register 0x400 read-only n 0x7990477 0xFFFFFFFF CLK_BBGEN_DIV_CLK BBGEN Divider Clock 0x8 read-write n 0x28 0xFFFFFFFF BBGEN_DIV Bbgen divider value 0 8 CLK_CTRL_ENABLE Clock Control Enable Register 0x30 read-write n 0xFFFF 0xFFFFFFFF ctrl_enable_clk1hz rtc_div_clk enable 0 1 ctrl_enable_dapswclk dapsw_mux_clk enable 1 2 ctrl_enable_gpiohclk I_SYSSYSUGCLK enable 2 3 ctrl_enable_i2sclk0 I_SYSSYSUGCLK enable 3 4 ctrl_enable_i2sclk1 I_SYSSYSUGCLK enable 4 5 ctrl_enable_i2sclk2 I_SYSSYSUGCLK enable 5 6 ctrl_enable_mainclk main_mux_clk enable 8 9 ctrl_enable_qspiphyclk qspi_div_clk enable 9 10 ctrl_enable_refclk ref_mux_clk enable 10 11 ctrl_enable_rm38kclk rm38k_mux_clk enable 11 12 ctrl_enable_sccclk scc_mux_clk enable 12 13 ctrl_enable_taptck tck_mux_clk enable 14 15 ctrl_enable_testclk test_div_clk enable 15 16 CLK_CTRL_SEL Clock Control Select Register 0x0 read-write n 0x62 0xFFFFFFFF CTRL_PLL_MUX_CLK_SEL PLL MUX select: 0: PLL0, 1: Not used 12 13 CTRL_SEL_TEST_MUX_CLK Select TESTMUX input 7 12 SEL_DAPSWMUX_CLK Select DAPSWMUX input: 0: PRE_MUX_CLK, 1: JTAG TCK 1 2 SEL_MAINMUX_CLK Select MAINMUX input: 0: PLL0_CLK, 1: PRE_MUX_CLK 2 3 SEL_PREMUX_CLK Select PREMUX input: 0: 32K, 1: FASTCLK 0 1 SEL_REFMUX_CLK Select REFMUX input: 0: PRE_MUX_CLK, 1: PRE_PLL_CLK 3 4 SEL_RM38KMUX_CLK Select RM38KMUX input: 0: REF_MUX_CLK, 1: RM38K (not used) 4 5 SEL_RM38P4_PREMUX_CLK Select RM38KPREMUX input: 0: SYSSYSSUGCLK, 1: NRM138P4 (not used) 6 7 SEL_SCCMUX_CLK Select SCCMUX input: 0: SCCCLK, 1: PRE_MUX_CLK 5 6 CLK_PLL_PREDIV_CTRL PLL Predivider Control Register 0x4 read-write n 0x0 0xFFFFFFFF PREDIV_CTRL PLL0 pre-divider value: Divison value = PREDIV_CTRL+1 0 10 CLK_POSTDIV_QSPI QSPI Divider 0x10 read-write n 0x0 0xFFFFFFFF postdiv_ctrl_qspi_div_clk qspi_div_clk value 0 8 CLK_POSTDIV_RTC RTC Divider 0x14 read-write n 0x7FFF 0xFFFFFFFF postdiv_ctrl_rtc_div_clk rtc_div_clk value 0 32 CLK_POSTDIV_TEST Test Divider 0x1C read-write n 0xA 0xFFFFFFFF postdiv_ctrl_test_div_clk test_div_clk value 0 8 CLK_STATUS Clock Status Register 0x34 read-only n 0x1 0xFFFFFFFF status_lock_signal_pll0_clk PLL Lock Status 1 2 status_out_clk_mainclk_ready Clock ready (active) 0 1 CPU0_VTOR CPU 0 VTOR Register 0x58 read-write n 0x10000000 0xFFFFFFFF CPU0_VTOR_1 CPU 0 VTOR 1 Register 0x5C read-write n 0x1A000000 0xFFFFFFFF CPU1_VTOR CPU 1 VTROR Register 0x60 read-write n 0x10000000 0xFFFFFFFF CPU1_VTOR_1 CPU 1 VTOR 1 Register 0x64 read-write n 0x1A000000 0xFFFFFFFF CTRL_BYPASS_DIV Bypass Divider Control Register 0x20 read-write n 0x1 0xFFFFFFFF ctrl_bypass_div_pll_prediv_clk pll_prediv_clk bypass value 0 1 ctrl_bypass_div_qspi_div_clk qspi_div_clk bypass value 3 4 ctrl_bypass_div_rtc_div_clk rtc_div_clk bypass value 4 5 ctrl_bypass_div_test_div_clk test_div_clk bypass value 6 7 DBG_CTRL Debug Control Register 0x48 read-write n 0x1F 0xFFFFFFFF DBGENIN Castor DBGENIN 0 1 dbg_dcu_force Castor DBG ports control 0: use Crypto DCU 1: Use SCC signals (force) 31 32 NIDENIN Castor NIDENIN 1 2 SPIDENIN Castor SPIDENIN 2 3 SPNIDENIN Castor SPNIDENIN 3 4 TODBGENSEL Debug expansion TODBGENSEL 8 8 INTR_CTRL MPC Interrupt Control Register 0x50 read-write n 0x0 0xFFFFFFFF mram_mpc_cfg_init_value mram mpc cfg init value 2 3 qspi_mpc_cfg_init_value qspi mpc cfg init value 1 2 sram_mpc_cfg_init_value sram mpc cfg init value 0 1 IOMUX_ALTF1_DEFAULT_IN IOMux Alternate Function 1 Input Default Data Register 0xA0 read-write n 0x0 0xFFFFFFFF IOMUX_ALTF1_INSEL IOMux Alternate Function 1 Input Data Select Register 0x88 read-write n 0x0 0xFFFFFFFF IOMUX_ALTF1_OENSEL IOMux Alternate Function 1 Output Enable Select Register 0x98 read-write n 0xFFFFFFFF 0xFFFFFFFF IOMUX_ALTF1_OUTSEL IOMux Alternate Function 1 Output Data Select Register 0x90 read-write n 0xFFFFFFFF 0xFFFFFFFF IOMUX_ALTF2_DEFAULT_IN IOMux Alternate Function 1 Input Default Data Register 0xC0 read-write n 0x0 0xFFFFFFFF IOMUX_ALTF2_INSEL IOMux Alternate Function 2 Input Data Select Register 0xA8 read-write n 0x0 0xFFFFFFFF IOMUX_ALTF2_OENSEL IOMux Alternate Function 2 Output Enable Select Register 0xB8 read-write n 0xFFFFFFFF 0xFFFFFFFF IOMUX_ALTF2_OUTSEL IOMux Alternate Function 2 Output Data Select Register 0xB0 read-write n 0xFFFFFFFF 0xFFFFFFFF IOMUX_ALTF3_DEFAULT_IN IOMux Alternate Function 1 Input Default Data Register 0xE0 read-write n 0x0 0xFFFFFFFF IOMUX_ALTF3_INSEL IOMux Alternate Function 3 Input Data Select Register 0xC8 read-write n 0x0 0xFFFFFFFF IOMUX_ALTF3_OENSEL IOMux Alternate Function 3 Output Enable Select Register 0xD8 read-write n 0xFFFFFFFF 0xFFFFFFFF IOMUX_ALTF3_OUTSEL IOMux Alternate Function 3 Output Data Select Register 0xD0 read-write n 0xFFFFFFFF 0xFFFFFFFF IOMUX_MAIN_DEFAULT_IN IOMux Main Function Input Default Data Register 0x80 read-write n 0x0 0xFFFFFFFF IOMUX_MAIN_INSEL IOMux Main Function Input Data Select Register 0x68 read-write n 0xFFFFFFFF 0xFFFFFFFF IOMUX_MAIN_OENSEL IOMux Main Function Output Enable Select Register 0x78 read-write n 0xFFFFFFFF 0xFFFFFFFF IOMUX_MAIN_OUTSEL IOMux Main Function Output Data Select Register 0x70 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_DS0 IO Pad Drive Select 0 Register 0xE8 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_DS1 IO Pad Drive Select 1 Register 0xF0 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_IS IO Pad Input Mode Select Register 0x110 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_PE IO Pad Pull Enable Register 0xF8 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_PS IO Pad Pull Select Register 0x100 read-write n 0xFC1FFFFF 0xFFFFFFFF IOPAD_SR IO Pad Slew Rate Register 0x108 read-write n 0x0 0xFFFFFFFF IO_IN_STATUS GP IO Pads Input Status Register 0x404 read-only n 0x13FFFFF 0xFFFFFFFF MRAM_CTRL0 eMRAM Control 0 Register 0x198 read-write n 0x40144003 0xFFFFFFFF autostop_en Auto stop enable 2 3 csn_high_clks Number of clock cycles to wait when CSN is high before going to new access 16 20 fast_read_en Fast read enable 4 5 mram_clk_en eMRAM clock enable 0 1 mram_clk_sync_bypass eMRAM clock sync bypass 30 31 mram_da_en eMRAM direct access enable 31 32 mram_dout_sel eMRAM data out select 6 6 mram_inv_clk_sel eMRAM clock invert select 3 4 mram_otp_clk_en eMRAM OTP clock enable 29 30 PG_VDD18_0 eMRAM0 PG VDD18 9 10 PG_VDD18_1 eMRAM1 PG VDD18 11 12 PG_VDD_0 eMRAM0 PG VDD 8 9 PG_VDD_1 eMRAM1 PG VDD 10 11 proc_spec_clk_en eMRAM controller clock enable 1 2 read_csn_clks Number of clocks cycles for single read operation 20 24 write_csn_clks Number of clock cycles for single write operation 12 16 MRAM_CTRL1 eMRAM Control 1 Register 0x19C read-write n 0x0 0xFFFFFFFF mram_da_addr eMRAM direct access address 0 24 mram_da_ctrl eMRAM direct access controls 24 32 MRAM_CTRL2 eMRAM Control 2 Register 0x1A0 read-write n 0xFFFF0119 0xFFFFFFFF mram_clk_div eMRAM clock divider 8 16 prescale eMRAM clock frequency value 0 8 time_to_stop Number of useconds to wait in inactive mode before going to STOP mode if auto_stop is enabled 16 32 MRAM_CTRL3 eMRAM Control 3 Register 0x1A4 read-write n 0x20 0xFFFFFFFF CaptureWR Access by SCC at functional mode 19 20 DA0 Access by SCC at functional mode 9 10 DA1 Access by SCC at functional mode 10 11 mram_load_rstn Access by SCC at functional mode 31 32 mram_load_start Access by SCC at functional mode 30 31 mram_resetb Access by SCC at functional mode 29 30 mram_stop Access by SCC at functional mode 28 29 M_SEL Access by SCC at functional mode 8 9 PDN_SCAN Access by SCC at functional mode 13 14 PG_VDD18_TM Access by SCC at functional mode 7 8 PG_VDD_TM Access by SCC at functional mode 6 7 RBACT1 Access by SCC at functional mode 20 21 RESETB_TM Access by SCC at functional mode 5 6 SCAN_MODE Access by SCC at functional mode 11 12 SelectWIR Access by SCC at functional mode 18 19 ShiftWR Access by SCC at functional mode 17 18 STOP_TM Access by SCC at functional mode 4 5 TEST_MODE Access by SCC at functional mode 0 3 TST_SCANENABLE Access by SCC at functional mode 12 13 TST_SCANIN Access by SCC at functional mode 23 28 UpdateWR Access by SCC at functional mode 21 22 WRCK Access by SCC at functional mode 16 17 WRSTN Access by SCC at functional mode 3 4 WSI Access by SCC at functional mode 22 23 MRAM_CTRL4 eMRAM Control 4 Register 0x1A8 read-write n 0x100002 0xFFFFFFFF Capture_OTP_LOAD_TM Access by SCC at functional mode 18 19 CK_TM Access by SCC at functional mode 0 1 CSN_TM Access by SCC at functional mode 1 2 DIN_DA_SPLIT Access by SCC at functional mode 4 12 DQ_SEL Access by SCC at functional mode 12 16 OTP_LOAD_RSTn_TM Access by SCC at functional mode 16 17 OTP_LOAD_START_TM Access by SCC at functional mode 17 18 REG_CLK Access by SCC at functional mode 19 20 REG_RESET Access by SCC at functional mode 20 21 TCK Access by SCC at functional mode 25 26 TDI Access by SCC at functional mode 26 27 TMS Access by SCC at functional mode 27 28 TRST Access by SCC at functional mode 28 29 WEN_TM Access by SCC at functional mode 2 3 XA_CNT Access by SCC at functional mode 21 22 XA_CNT_SEL Access by SCC at functional mode 22 23 XA_ShiftorCapture Access by SCC at functional mode 23 24 XA_SI Access by SCC at functional mode 24 25 MRAM_DIN0 eMRAM input data mram_din[31:0] 0x1B0 read-write n 0x0 0xFFFFFFFF MRAM_DIN1 eMRAM input data mram_din[63:32] 0x1B4 read-write n 0x0 0xFFFFFFFF MRAM_DIN2 eMRAM input data mram_din[77:64] 0x1B8 read-write n 0x0 0xFFFFFFFF MRAM_DOUT0 eMRAM output data mram_dout[31:0] 0x1C0 read-only n 0x0 0xFFFFFFFF MRAM_DOUT1 eMRAM output data mram_dout[63:32] 0x1C4 read-only n 0x0 0xFFFFFFFF MRAM_DOUT2 eMRAM output data mram_dout[77:64] 0x1C8 read-only n 0x0 0xFFFFFFFF MRAM_STATUS eMRAM Status Register 0x1CC read-only n 0x0 0xFFFFFFFF fsm_state eMRAM controller FSM state 0 5 mram_test_mode eMRAM test mode 5 8 PCSM_CTRL_OVEERIDE PCSM Control Override Register 0x148 read-write n 0x0 0xFFFFFFFF BCRYPTOSPIKCLKQACTIVE Q-Channels QACTIVE Override 3 4 CRYPTOPWRQACTIVE Q-Channels QACTIVE Override 4 5 CRYPTOSYSCLKQACTIVE Q-Channels QACTIVE Override 2 3 DBGPWRQACTIVE Q-Channels QACTIVE Override 7 8 DBGPWRQACTIVE_en Q-Channels QACTIVE Override 9 10 DEBUGPIKCLKQACTIVE Q-Channels QACTIVE Override 6 7 DEBUGPIKCLKQACTIVE_en Q-Channels QACTIVE Override 8 9 SYSFCLKQACTIVE Q-Channels QACTIVE Override 1 2 SYSPWRQACTIVE Q-Channels QACTIVE Override 5 6 SYSSYSCLKQACTIVE Q-Channels QACTIVE Override 0 1 PD_CPU0_ISO_OVEERIDE 0x14C read-write n 0x0 0xFFFFFFFF CHSEC_BYPASS Secure Frame Bypass 2 3 CHSEC_DISCHARGE_CNTL Secure Frame discharge control 3 4 CHSEC_FREQ_SEL Secure Frame Frequency select 0 2 CHSEC_ISO_ENB Secure Frame Isolation Enable 5 6 CHSEC_MISC Secure Frame Control 8 16 CHSEC_SE_CNTL Secure Frame Scan Enable control 4 5 PD_CPU1_ISO_OVEERIDE CPU1 Isolation Override Register 0x150 read-write n 0x0 0xFFFFFFFF PLL_CTRL_PLL0_CLK PLL0 Control Register 0x24 read-write n 0x1005F4 0xFFFFFFFF Pll0_AFC_ENB Monitoring pin 28 29 Pll0_BYPASS bypass mode 29 30 Pll0_EXTAFC Monitoring pin 16 21 Pll0_M Control pins to change the target frequency of internal oscillator 0 12 Pll0_RESETB Power down 31 32 Pll0_S Division value of the 3-bit programmable scaler 12 15 Pll1_RESETB Power down 30 31 PVT_CTRL PVT Control Register 0x118 read-write n 0x0 0xFFFFFFFF TSTGRPSEL Test group select 5 6 TSTSENNUM Test SEN number 0 5 REQ_CLEAR Clock and Power Request Clear Register 0x144 read-write n 0x0 0xFFFFFFFF clk_req_clear Clock request clear 0 1 pwr_req_clear Power request clear 1 5 REQ_EDGE_SEL Clock and Power Request Edge Select Register 0x184 read-write n 0x0 0xFFFFFFFF REQ_ENABLE Clock and Power Request Enable Register 0x188 read-write n 0x0 0xFFFFFFFF REQ_SET Clock and Power Request Set Register 0x140 read-write n 0x1 0xFFFFFFFF clk_req_set Set SYSMAINCLKREQUEST 0 1 pwr_req_set Set SYSPOWERREQUEST 1 5 pwr_req_set_en External event enable 8 12 RESET_CTRL Reset Control Register 0x40 read-write n 0xFFFFFFFF 0xFFFFFFFF CASTOR_NSRST Reset Active low 17 18 CASTOR_NSRST_PSI_Sel Reset Active low 15 16 CASTOR_NSRST_Sel Reset Active low 16 17 GPIO_RESET Reset Active low 9 10 GPTIMER_RESET Reset Active low 1 2 I2C0_RESET Reset Active low 2 3 I2C1_RESET Reset Active low 3 4 I2S_RESET Reset Active low 4 5 PVT_RESET Reset Active low 10 11 PWM0_RESET Reset Active low 11 12 PWM1_RESET Reset Active low 12 13 PWM2_RESET Reset Active low 13 14 QSPI_RESET Reset Active low 6 7 RTC_RESET Reset Active low 14 15 SPI_RESET Reset Active low 5 6 UART0_RESET Reset Active low 7 8 UART1_RESET Reset Active low 8 9 SELECTION_CONTROL_REG Selection Control Register 0x1E0 read-write n 0x1000200 0xFFFFFFFF Clock_phase_shifter_bypass Clock phase shifter bypass 2 3 Clock_phase_shifter_select Clock phase shifter select 1 1 SPARE_CTRL1 Spare 1 Control Register 0x224 read-write n 0x0 0xFFFFFFFF SRAM_CTRL SRAM Control Register 0x4C read-write n 0x0 0xFFFFFFFF code_sram0_pgen 1st 64KB Code SRAM cell power gate enable 0 1 code_sram10_pgen 11st 64KB Code SRAM cell power gate enable 10 11 code_sram11_pgen 12th 64KB Code SRAM cell power gate enable 11 12 code_sram12_pgen 13th 64KB Code SRAM cell power gate enable 12 13 code_sram13_pgen 14th 64KB Code SRAM cell power gate enable 13 14 code_sram14_pgen 15th 64KB Code SRAM cell power gate enable 14 15 code_sram15_pgen 16th 64KB Code SRAM cell power gate enable 15 16 code_sram16_pgen 17th 64KB Code SRAM cell power gate enable 16 17 code_sram17_pgen 18th 64KB Code SRAM cell power gate enable 17 18 code_sram18_pgen 19th 64KB Code SRAM cell power gate enable 18 19 code_sram19_pgen 20th 64KB Code SRAM cell power gate enable 19 20 code_sram1_pgen 2nd 64KB Code SRAM cell power gate enable 1 2 code_sram20_pgen 21st 64KB Code SRAM cell power gate enable 20 21 code_sram21_pgen 22th 64KB Code SRAM cell power gate enable 21 22 code_sram22_pgen 23th 64KB Code SRAM cell power gate enable 22 23 code_sram23_pgen 24th 64KB Code SRAM cell power gate enable 23 24 code_sram24_pgen 25th 64KB Code SRAM cell power gate enable 24 25 code_sram25_pgen 26th 64KB Code SRAM cell power gate enable 25 26 code_sram26_pgen 27th 64KB Code SRAM cell power gate enable 26 27 code_sram27_pgen 28th 64KB Code SRAM cell power gate enable 27 28 code_sram28_pgen 29th 64KB Code SRAM cell power gate enable 28 29 code_sram29_pgen 30th 64KB Code SRAM cell power gate enable 29 30 code_sram2_pgen 3rd 64KB Code SRAM cell power gate enable 2 3 code_sram30_pgen 31st 64KB Code SRAM cell power gate enable 30 31 code_sram31_pgen 32th 64KB Code SRAM cell power gate enable 31 32 code_sram3_pgen 4th 64KB Code SRAM cell power gate enable 3 4 code_sram4_pgen 5th 64KB Code SRAM cell power gate enable 4 5 code_sram5_pgen 6th 64KB Code SRAM cell power gate enable 5 6 code_sram6_pgen 7th 64KB Code SRAM cell power gate enable 6 7 code_sram7_pgen 8th 64KB Code SRAM cell power gate enable 7 8 code_sram8_pgen 9th 64KB Code SRAM cell power gate enable 8 9 code_sram9_pgen 10th 64KB Code SRAM cell power gate enable 9 10 SRAM_RW_MARGINE SRAM Read/Write Margin Control Register 0x134 read-write n 0x0 0xFFFFFFFF RM0 Read margin control for code srams: u_sram_64k_0 .. u_sram_64k_7 0 3 RM1 Read margin control for code srams: u_sram_64k_8 .. u_sram_64k_15 8 11 RM2 Read margin control for code srams: u_sram_64k_16 .. u_sram_64k_23 16 19 RM3 Read margin control for code srams: u_sram_64k_24 .. u_sram_64k_31 24 27 WM0 Write margin control for code srams: u_sram_64k_0 .. u_sram_64k_7 4 6 WM1 Write margin control for code srams: u_sram_64k_8 .. u_sram_64k_15 12 14 WM2 Write margin control for code srams: u_sram_64k_16 .. u_sram_64k_23 20 22 WM3 Write margin control for code srams: u_sram_64k_24 .. u_sram_64k_31 28 30 STATIC_CONF_SIG0 0x138 read-write n 0x1E0 0xFFFFFFFF CTMCHCIHSBYPASS Cross Trigger Channel Interface Configuarion 1 5 CTMCHCISBYPASS Cross Trigger Channel Interface Configuration 0 1 DBGENSELDIS DBGEN Selector Disable 5 6 NIDENSELDIS NIDEN Selector Disable 6 7 SPIDENSELDIS SPIDEN Selector Disable 7 8 SPNIDENSELDIS SPNIDEN Selector Disable 8 9 STATIC_CONF_SIG1 0x13C read-write n 0x0 0xFFFFFFFF TIHSBYPASS Cross Trigger interface handshake bypass on CTITRIGOUT 12 16 TINIDENSEL NIDEN mask on CTITRIGINT 16 24 TISBYPASSACK Cross Trigger Interface synchronous bypass on CTITRIGOUTACK 8 12 TISBYPASSIN Cross Trigger Interface synchronous bypass on CTITRIGIN 0 8 TODBGENSEL DBGEN mask on CTITRIGOUT 24 28 SYS_SRAM_RW_ASSIST0 CPU0 SRAM Read/Write Margin Control Register 0x154 read-write n 0x0 0xFFFFFFFF RM0 Castor cpu0 tag_sram_0 read margin 0 3 RM1 Castor cpu0 tag_sram_1 read margin 16 19 WM0 Castor cpu0 tag_sram_0 write margin 4 6 WM1 Castor cpu0 tag_sram_1 write margin 20 22 SYS_SRAM_RW_ASSIST1 CPU1 SRAM Read/Write Margin Control Register 0x158 read-write n 0x0 0xFFFFFFFF RM0 Castor cpu1 tag_sram_0 read margin 0 3 RM1 Castor cpu1 tag_sram_1 read margin 16 19 WM0 Castor cpu1 tag_sram_0 write margin 4 6 WM1 Castor cpu1 tag_sram_1 write margin 20 22 SYS_SRAM_RW_ASSIST4 Core 0/1 SRAM Read/Write Margin Control Register 0x164 read-write n 0x0 0xFFFFFFFF RM0 Castor core_0 sram_0 read margin 0 3 RM1 Castor core_0 sram_1 read margin 8 11 RM2 Castor core_1 sram_0 read margin 16 19 RM3 Castor core_1 sram_1 read margin 24 27 WM0 Castor core_0 sram_0 write margin 4 6 WM1 Castor core_0 sram_1 write margin 12 14 WM2 Castor core_1 sram_0 write margin 20 22 WM3 Castor core_1 sram_1 write margin 28 30 SYS_SRAM_RW_ASSIST5 Core 2/3 SRAM Read/Write Margin Control Register 0x168 read-write n 0x0 0xFFFFFFFF RM0 Castor core_2 sram_0 read margin 0 3 RM1 Castor core_2 sram_1 read margin 8 11 RM2 Castor core_3 sram_0 read margin 16 19 RM3 Castor core_3 sram_1 read margin 24 27 WM0 Castor core_2 sram_0 write margin 4 6 WM1 Castor core_2 sram_1 write margin 12 14 WM2 Castor core_3 sram_0 write margin 20 22 WM3 Castor core_3 sram_1 write margin 28 30 SCC_Secure Serial Communication Controller (Secure) SCC 0x5010C800 0x0 0x1000 registers n AZ_CTRL AZ Control Register 0x200 read-write n 0x0 0xFFFFFFFF SCC_nPORESETAON_nPORESET_SEL Memory subsystem reset select: 1: nPORESETAON 0: NPORESET 9 10 BBGEN_CTRL Body Bias Enable Control Register 0x220 read-write n 0x0 0xFFFFFFFF CASTOR_OTP_CTRL OTP Control Register 0x204 read-write n 0x0 0xFFFFFFFF pad_sel OTP control selection 30 31 scc_addr otp addr from scc 0 16 scc_din din from scc 16 17 scc_otp_ctrl scc otp control 20 30 scc_readen readen from scc 18 19 scc_sel OTP control selection 31 32 scc_web web from scc 17 18 CHIP_ID Chip ID Register 0x400 read-only n 0x7990477 0xFFFFFFFF CLK_BBGEN_DIV_CLK BBGEN Divider Clock 0x8 read-write n 0x28 0xFFFFFFFF BBGEN_DIV Bbgen divider value 0 8 CLK_CTRL_ENABLE Clock Control Enable Register 0x30 read-write n 0xFFFF 0xFFFFFFFF ctrl_enable_clk1hz rtc_div_clk enable 0 1 ctrl_enable_dapswclk dapsw_mux_clk enable 1 2 ctrl_enable_gpiohclk I_SYSSYSUGCLK enable 2 3 ctrl_enable_i2sclk0 I_SYSSYSUGCLK enable 3 4 ctrl_enable_i2sclk1 I_SYSSYSUGCLK enable 4 5 ctrl_enable_i2sclk2 I_SYSSYSUGCLK enable 5 6 ctrl_enable_mainclk main_mux_clk enable 8 9 ctrl_enable_qspiphyclk qspi_div_clk enable 9 10 ctrl_enable_refclk ref_mux_clk enable 10 11 ctrl_enable_rm38kclk rm38k_mux_clk enable 11 12 ctrl_enable_sccclk scc_mux_clk enable 12 13 ctrl_enable_taptck tck_mux_clk enable 14 15 ctrl_enable_testclk test_div_clk enable 15 16 CLK_CTRL_SEL Clock Control Select Register 0x0 read-write n 0x62 0xFFFFFFFF CTRL_PLL_MUX_CLK_SEL PLL MUX select: 0: PLL0, 1: Not used 12 13 CTRL_SEL_TEST_MUX_CLK Select TESTMUX input 7 12 SEL_DAPSWMUX_CLK Select DAPSWMUX input: 0: PRE_MUX_CLK, 1: JTAG TCK 1 2 SEL_MAINMUX_CLK Select MAINMUX input: 0: PLL0_CLK, 1: PRE_MUX_CLK 2 3 SEL_PREMUX_CLK Select PREMUX input: 0: 32K, 1: FASTCLK 0 1 SEL_REFMUX_CLK Select REFMUX input: 0: PRE_MUX_CLK, 1: PRE_PLL_CLK 3 4 SEL_RM38KMUX_CLK Select RM38KMUX input: 0: REF_MUX_CLK, 1: RM38K (not used) 4 5 SEL_RM38P4_PREMUX_CLK Select RM38KPREMUX input: 0: SYSSYSSUGCLK, 1: NRM138P4 (not used) 6 7 SEL_SCCMUX_CLK Select SCCMUX input: 0: SCCCLK, 1: PRE_MUX_CLK 5 6 CLK_PLL_PREDIV_CTRL PLL Predivider Control Register 0x4 read-write n 0x0 0xFFFFFFFF PREDIV_CTRL PLL0 pre-divider value: Divison value = PREDIV_CTRL+1 0 10 CLK_POSTDIV_QSPI QSPI Divider 0x10 read-write n 0x0 0xFFFFFFFF postdiv_ctrl_qspi_div_clk qspi_div_clk value 0 8 CLK_POSTDIV_RTC RTC Divider 0x14 read-write n 0x7FFF 0xFFFFFFFF postdiv_ctrl_rtc_div_clk rtc_div_clk value 0 32 CLK_POSTDIV_TEST Test Divider 0x1C read-write n 0xA 0xFFFFFFFF postdiv_ctrl_test_div_clk test_div_clk value 0 8 CLK_STATUS Clock Status Register 0x34 read-only n 0x1 0xFFFFFFFF status_lock_signal_pll0_clk PLL Lock Status 1 2 status_out_clk_mainclk_ready Clock ready (active) 0 1 CPU0_VTOR CPU 0 VTOR Register 0x58 read-write n 0x10000000 0xFFFFFFFF CPU0_VTOR_1 CPU 0 VTOR 1 Register 0x5C read-write n 0x1A000000 0xFFFFFFFF CPU1_VTOR CPU 1 VTROR Register 0x60 read-write n 0x10000000 0xFFFFFFFF CPU1_VTOR_1 CPU 1 VTOR 1 Register 0x64 read-write n 0x1A000000 0xFFFFFFFF CTRL_BYPASS_DIV Bypass Divider Control Register 0x20 read-write n 0x1 0xFFFFFFFF ctrl_bypass_div_pll_prediv_clk pll_prediv_clk bypass value 0 1 ctrl_bypass_div_qspi_div_clk qspi_div_clk bypass value 3 4 ctrl_bypass_div_rtc_div_clk rtc_div_clk bypass value 4 5 ctrl_bypass_div_test_div_clk test_div_clk bypass value 6 7 DBG_CTRL Debug Control Register 0x48 read-write n 0x1F 0xFFFFFFFF DBGENIN Castor DBGENIN 0 1 dbg_dcu_force Castor DBG ports control 0: use Crypto DCU 1: Use SCC signals (force) 31 32 NIDENIN Castor NIDENIN 1 2 SPIDENIN Castor SPIDENIN 2 3 SPNIDENIN Castor SPNIDENIN 3 4 TODBGENSEL Debug expansion TODBGENSEL 8 8 INTR_CTRL MPC Interrupt Control Register 0x50 read-write n 0x0 0xFFFFFFFF mram_mpc_cfg_init_value mram mpc cfg init value 2 3 qspi_mpc_cfg_init_value qspi mpc cfg init value 1 2 sram_mpc_cfg_init_value sram mpc cfg init value 0 1 IOMUX_ALTF1_DEFAULT_IN IOMux Alternate Function 1 Input Default Data Register 0xA0 read-write n 0x0 0xFFFFFFFF IOMUX_ALTF1_INSEL IOMux Alternate Function 1 Input Data Select Register 0x88 read-write n 0x0 0xFFFFFFFF IOMUX_ALTF1_OENSEL IOMux Alternate Function 1 Output Enable Select Register 0x98 read-write n 0xFFFFFFFF 0xFFFFFFFF IOMUX_ALTF1_OUTSEL IOMux Alternate Function 1 Output Data Select Register 0x90 read-write n 0xFFFFFFFF 0xFFFFFFFF IOMUX_ALTF2_DEFAULT_IN IOMux Alternate Function 1 Input Default Data Register 0xC0 read-write n 0x0 0xFFFFFFFF IOMUX_ALTF2_INSEL IOMux Alternate Function 2 Input Data Select Register 0xA8 read-write n 0x0 0xFFFFFFFF IOMUX_ALTF2_OENSEL IOMux Alternate Function 2 Output Enable Select Register 0xB8 read-write n 0xFFFFFFFF 0xFFFFFFFF IOMUX_ALTF2_OUTSEL IOMux Alternate Function 2 Output Data Select Register 0xB0 read-write n 0xFFFFFFFF 0xFFFFFFFF IOMUX_ALTF3_DEFAULT_IN IOMux Alternate Function 1 Input Default Data Register 0xE0 read-write n 0x0 0xFFFFFFFF IOMUX_ALTF3_INSEL IOMux Alternate Function 3 Input Data Select Register 0xC8 read-write n 0x0 0xFFFFFFFF IOMUX_ALTF3_OENSEL IOMux Alternate Function 3 Output Enable Select Register 0xD8 read-write n 0xFFFFFFFF 0xFFFFFFFF IOMUX_ALTF3_OUTSEL IOMux Alternate Function 3 Output Data Select Register 0xD0 read-write n 0xFFFFFFFF 0xFFFFFFFF IOMUX_MAIN_DEFAULT_IN IOMux Main Function Input Default Data Register 0x80 read-write n 0x0 0xFFFFFFFF IOMUX_MAIN_INSEL IOMux Main Function Input Data Select Register 0x68 read-write n 0xFFFFFFFF 0xFFFFFFFF IOMUX_MAIN_OENSEL IOMux Main Function Output Enable Select Register 0x78 read-write n 0xFFFFFFFF 0xFFFFFFFF IOMUX_MAIN_OUTSEL IOMux Main Function Output Data Select Register 0x70 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_DS0 IO Pad Drive Select 0 Register 0xE8 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_DS1 IO Pad Drive Select 1 Register 0xF0 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_IS IO Pad Input Mode Select Register 0x110 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_PE IO Pad Pull Enable Register 0xF8 read-write n 0xFFFFFFFF 0xFFFFFFFF IOPAD_PS IO Pad Pull Select Register 0x100 read-write n 0xFC1FFFFF 0xFFFFFFFF IOPAD_SR IO Pad Slew Rate Register 0x108 read-write n 0x0 0xFFFFFFFF IO_IN_STATUS GP IO Pads Input Status Register 0x404 read-only n 0x13FFFFF 0xFFFFFFFF MRAM_CTRL0 eMRAM Control 0 Register 0x198 read-write n 0x40144003 0xFFFFFFFF autostop_en Auto stop enable 2 3 csn_high_clks Number of clock cycles to wait when CSN is high before going to new access 16 20 fast_read_en Fast read enable 4 5 mram_clk_en eMRAM clock enable 0 1 mram_clk_sync_bypass eMRAM clock sync bypass 30 31 mram_da_en eMRAM direct access enable 31 32 mram_dout_sel eMRAM data out select 6 6 mram_inv_clk_sel eMRAM clock invert select 3 4 mram_otp_clk_en eMRAM OTP clock enable 29 30 PG_VDD18_0 eMRAM0 PG VDD18 9 10 PG_VDD18_1 eMRAM1 PG VDD18 11 12 PG_VDD_0 eMRAM0 PG VDD 8 9 PG_VDD_1 eMRAM1 PG VDD 10 11 proc_spec_clk_en eMRAM controller clock enable 1 2 read_csn_clks Number of clocks cycles for single read operation 20 24 write_csn_clks Number of clock cycles for single write operation 12 16 MRAM_CTRL1 eMRAM Control 1 Register 0x19C read-write n 0x0 0xFFFFFFFF mram_da_addr eMRAM direct access address 0 24 mram_da_ctrl eMRAM direct access controls 24 32 MRAM_CTRL2 eMRAM Control 2 Register 0x1A0 read-write n 0xFFFF0119 0xFFFFFFFF mram_clk_div eMRAM clock divider 8 16 prescale eMRAM clock frequency value 0 8 time_to_stop Number of useconds to wait in inactive mode before going to STOP mode if auto_stop is enabled 16 32 MRAM_CTRL3 eMRAM Control 3 Register 0x1A4 read-write n 0x20 0xFFFFFFFF CaptureWR Access by SCC at functional mode 19 20 DA0 Access by SCC at functional mode 9 10 DA1 Access by SCC at functional mode 10 11 mram_load_rstn Access by SCC at functional mode 31 32 mram_load_start Access by SCC at functional mode 30 31 mram_resetb Access by SCC at functional mode 29 30 mram_stop Access by SCC at functional mode 28 29 M_SEL Access by SCC at functional mode 8 9 PDN_SCAN Access by SCC at functional mode 13 14 PG_VDD18_TM Access by SCC at functional mode 7 8 PG_VDD_TM Access by SCC at functional mode 6 7 RBACT1 Access by SCC at functional mode 20 21 RESETB_TM Access by SCC at functional mode 5 6 SCAN_MODE Access by SCC at functional mode 11 12 SelectWIR Access by SCC at functional mode 18 19 ShiftWR Access by SCC at functional mode 17 18 STOP_TM Access by SCC at functional mode 4 5 TEST_MODE Access by SCC at functional mode 0 3 TST_SCANENABLE Access by SCC at functional mode 12 13 TST_SCANIN Access by SCC at functional mode 23 28 UpdateWR Access by SCC at functional mode 21 22 WRCK Access by SCC at functional mode 16 17 WRSTN Access by SCC at functional mode 3 4 WSI Access by SCC at functional mode 22 23 MRAM_CTRL4 eMRAM Control 4 Register 0x1A8 read-write n 0x100002 0xFFFFFFFF Capture_OTP_LOAD_TM Access by SCC at functional mode 18 19 CK_TM Access by SCC at functional mode 0 1 CSN_TM Access by SCC at functional mode 1 2 DIN_DA_SPLIT Access by SCC at functional mode 4 12 DQ_SEL Access by SCC at functional mode 12 16 OTP_LOAD_RSTn_TM Access by SCC at functional mode 16 17 OTP_LOAD_START_TM Access by SCC at functional mode 17 18 REG_CLK Access by SCC at functional mode 19 20 REG_RESET Access by SCC at functional mode 20 21 TCK Access by SCC at functional mode 25 26 TDI Access by SCC at functional mode 26 27 TMS Access by SCC at functional mode 27 28 TRST Access by SCC at functional mode 28 29 WEN_TM Access by SCC at functional mode 2 3 XA_CNT Access by SCC at functional mode 21 22 XA_CNT_SEL Access by SCC at functional mode 22 23 XA_ShiftorCapture Access by SCC at functional mode 23 24 XA_SI Access by SCC at functional mode 24 25 MRAM_DIN0 eMRAM input data mram_din[31:0] 0x1B0 read-write n 0x0 0xFFFFFFFF MRAM_DIN1 eMRAM input data mram_din[63:32] 0x1B4 read-write n 0x0 0xFFFFFFFF MRAM_DIN2 eMRAM input data mram_din[77:64] 0x1B8 read-write n 0x0 0xFFFFFFFF MRAM_DOUT0 eMRAM output data mram_dout[31:0] 0x1C0 read-only n 0x0 0xFFFFFFFF MRAM_DOUT1 eMRAM output data mram_dout[63:32] 0x1C4 read-only n 0x0 0xFFFFFFFF MRAM_DOUT2 eMRAM output data mram_dout[77:64] 0x1C8 read-only n 0x0 0xFFFFFFFF MRAM_STATUS eMRAM Status Register 0x1CC read-only n 0x0 0xFFFFFFFF fsm_state eMRAM controller FSM state 0 5 mram_test_mode eMRAM test mode 5 8 PCSM_CTRL_OVEERIDE PCSM Control Override Register 0x148 read-write n 0x0 0xFFFFFFFF BCRYPTOSPIKCLKQACTIVE Q-Channels QACTIVE Override 3 4 CRYPTOPWRQACTIVE Q-Channels QACTIVE Override 4 5 CRYPTOSYSCLKQACTIVE Q-Channels QACTIVE Override 2 3 DBGPWRQACTIVE Q-Channels QACTIVE Override 7 8 DBGPWRQACTIVE_en Q-Channels QACTIVE Override 9 10 DEBUGPIKCLKQACTIVE Q-Channels QACTIVE Override 6 7 DEBUGPIKCLKQACTIVE_en Q-Channels QACTIVE Override 8 9 SYSFCLKQACTIVE Q-Channels QACTIVE Override 1 2 SYSPWRQACTIVE Q-Channels QACTIVE Override 5 6 SYSSYSCLKQACTIVE Q-Channels QACTIVE Override 0 1 PD_CPU0_ISO_OVEERIDE 0x14C read-write n 0x0 0xFFFFFFFF CHSEC_BYPASS Secure Frame Bypass 2 3 CHSEC_DISCHARGE_CNTL Secure Frame discharge control 3 4 CHSEC_FREQ_SEL Secure Frame Frequency select 0 2 CHSEC_ISO_ENB Secure Frame Isolation Enable 5 6 CHSEC_MISC Secure Frame Control 8 16 CHSEC_SE_CNTL Secure Frame Scan Enable control 4 5 PD_CPU1_ISO_OVEERIDE CPU1 Isolation Override Register 0x150 read-write n 0x0 0xFFFFFFFF PLL_CTRL_PLL0_CLK PLL0 Control Register 0x24 read-write n 0x1005F4 0xFFFFFFFF Pll0_AFC_ENB Monitoring pin 28 29 Pll0_BYPASS bypass mode 29 30 Pll0_EXTAFC Monitoring pin 16 21 Pll0_M Control pins to change the target frequency of internal oscillator 0 12 Pll0_RESETB Power down 31 32 Pll0_S Division value of the 3-bit programmable scaler 12 15 Pll1_RESETB Power down 30 31 PVT_CTRL PVT Control Register 0x118 read-write n 0x0 0xFFFFFFFF TSTGRPSEL Test group select 5 6 TSTSENNUM Test SEN number 0 5 REQ_CLEAR Clock and Power Request Clear Register 0x144 read-write n 0x0 0xFFFFFFFF clk_req_clear Clock request clear 0 1 pwr_req_clear Power request clear 1 5 REQ_EDGE_SEL Clock and Power Request Edge Select Register 0x184 read-write n 0x0 0xFFFFFFFF REQ_ENABLE Clock and Power Request Enable Register 0x188 read-write n 0x0 0xFFFFFFFF REQ_SET Clock and Power Request Set Register 0x140 read-write n 0x1 0xFFFFFFFF clk_req_set Set SYSMAINCLKREQUEST 0 1 pwr_req_set Set SYSPOWERREQUEST 1 5 pwr_req_set_en External event enable 8 12 RESET_CTRL Reset Control Register 0x40 read-write n 0xFFFFFFFF 0xFFFFFFFF CASTOR_NSRST Reset Active low 17 18 CASTOR_NSRST_PSI_Sel Reset Active low 15 16 CASTOR_NSRST_Sel Reset Active low 16 17 GPIO_RESET Reset Active low 9 10 GPTIMER_RESET Reset Active low 1 2 I2C0_RESET Reset Active low 2 3 I2C1_RESET Reset Active low 3 4 I2S_RESET Reset Active low 4 5 PVT_RESET Reset Active low 10 11 PWM0_RESET Reset Active low 11 12 PWM1_RESET Reset Active low 12 13 PWM2_RESET Reset Active low 13 14 QSPI_RESET Reset Active low 6 7 RTC_RESET Reset Active low 14 15 SPI_RESET Reset Active low 5 6 UART0_RESET Reset Active low 7 8 UART1_RESET Reset Active low 8 9 SELECTION_CONTROL_REG Selection Control Register 0x1E0 read-write n 0x1000200 0xFFFFFFFF Clock_phase_shifter_bypass Clock phase shifter bypass 2 3 Clock_phase_shifter_select Clock phase shifter select 1 1 SPARE_CTRL1 Spare 1 Control Register 0x224 read-write n 0x0 0xFFFFFFFF SRAM_CTRL SRAM Control Register 0x4C read-write n 0x0 0xFFFFFFFF code_sram0_pgen 1st 64KB Code SRAM cell power gate enable 0 1 code_sram10_pgen 11st 64KB Code SRAM cell power gate enable 10 11 code_sram11_pgen 12th 64KB Code SRAM cell power gate enable 11 12 code_sram12_pgen 13th 64KB Code SRAM cell power gate enable 12 13 code_sram13_pgen 14th 64KB Code SRAM cell power gate enable 13 14 code_sram14_pgen 15th 64KB Code SRAM cell power gate enable 14 15 code_sram15_pgen 16th 64KB Code SRAM cell power gate enable 15 16 code_sram16_pgen 17th 64KB Code SRAM cell power gate enable 16 17 code_sram17_pgen 18th 64KB Code SRAM cell power gate enable 17 18 code_sram18_pgen 19th 64KB Code SRAM cell power gate enable 18 19 code_sram19_pgen 20th 64KB Code SRAM cell power gate enable 19 20 code_sram1_pgen 2nd 64KB Code SRAM cell power gate enable 1 2 code_sram20_pgen 21st 64KB Code SRAM cell power gate enable 20 21 code_sram21_pgen 22th 64KB Code SRAM cell power gate enable 21 22 code_sram22_pgen 23th 64KB Code SRAM cell power gate enable 22 23 code_sram23_pgen 24th 64KB Code SRAM cell power gate enable 23 24 code_sram24_pgen 25th 64KB Code SRAM cell power gate enable 24 25 code_sram25_pgen 26th 64KB Code SRAM cell power gate enable 25 26 code_sram26_pgen 27th 64KB Code SRAM cell power gate enable 26 27 code_sram27_pgen 28th 64KB Code SRAM cell power gate enable 27 28 code_sram28_pgen 29th 64KB Code SRAM cell power gate enable 28 29 code_sram29_pgen 30th 64KB Code SRAM cell power gate enable 29 30 code_sram2_pgen 3rd 64KB Code SRAM cell power gate enable 2 3 code_sram30_pgen 31st 64KB Code SRAM cell power gate enable 30 31 code_sram31_pgen 32th 64KB Code SRAM cell power gate enable 31 32 code_sram3_pgen 4th 64KB Code SRAM cell power gate enable 3 4 code_sram4_pgen 5th 64KB Code SRAM cell power gate enable 4 5 code_sram5_pgen 6th 64KB Code SRAM cell power gate enable 5 6 code_sram6_pgen 7th 64KB Code SRAM cell power gate enable 6 7 code_sram7_pgen 8th 64KB Code SRAM cell power gate enable 7 8 code_sram8_pgen 9th 64KB Code SRAM cell power gate enable 8 9 code_sram9_pgen 10th 64KB Code SRAM cell power gate enable 9 10 SRAM_RW_MARGINE SRAM Read/Write Margin Control Register 0x134 read-write n 0x0 0xFFFFFFFF RM0 Read margin control for code srams: u_sram_64k_0 .. u_sram_64k_7 0 3 RM1 Read margin control for code srams: u_sram_64k_8 .. u_sram_64k_15 8 11 RM2 Read margin control for code srams: u_sram_64k_16 .. u_sram_64k_23 16 19 RM3 Read margin control for code srams: u_sram_64k_24 .. u_sram_64k_31 24 27 WM0 Write margin control for code srams: u_sram_64k_0 .. u_sram_64k_7 4 6 WM1 Write margin control for code srams: u_sram_64k_8 .. u_sram_64k_15 12 14 WM2 Write margin control for code srams: u_sram_64k_16 .. u_sram_64k_23 20 22 WM3 Write margin control for code srams: u_sram_64k_24 .. u_sram_64k_31 28 30 STATIC_CONF_SIG0 0x138 read-write n 0x1E0 0xFFFFFFFF CTMCHCIHSBYPASS Cross Trigger Channel Interface Configuarion 1 5 CTMCHCISBYPASS Cross Trigger Channel Interface Configuration 0 1 DBGENSELDIS DBGEN Selector Disable 5 6 NIDENSELDIS NIDEN Selector Disable 6 7 SPIDENSELDIS SPIDEN Selector Disable 7 8 SPNIDENSELDIS SPNIDEN Selector Disable 8 9 STATIC_CONF_SIG1 0x13C read-write n 0x0 0xFFFFFFFF TIHSBYPASS Cross Trigger interface handshake bypass on CTITRIGOUT 12 16 TINIDENSEL NIDEN mask on CTITRIGINT 16 24 TISBYPASSACK Cross Trigger Interface synchronous bypass on CTITRIGOUTACK 8 12 TISBYPASSIN Cross Trigger Interface synchronous bypass on CTITRIGIN 0 8 TODBGENSEL DBGEN mask on CTITRIGOUT 24 28 SYS_SRAM_RW_ASSIST0 CPU0 SRAM Read/Write Margin Control Register 0x154 read-write n 0x0 0xFFFFFFFF RM0 Castor cpu0 tag_sram_0 read margin 0 3 RM1 Castor cpu0 tag_sram_1 read margin 16 19 WM0 Castor cpu0 tag_sram_0 write margin 4 6 WM1 Castor cpu0 tag_sram_1 write margin 20 22 SYS_SRAM_RW_ASSIST1 CPU1 SRAM Read/Write Margin Control Register 0x158 read-write n 0x0 0xFFFFFFFF RM0 Castor cpu1 tag_sram_0 read margin 0 3 RM1 Castor cpu1 tag_sram_1 read margin 16 19 WM0 Castor cpu1 tag_sram_0 write margin 4 6 WM1 Castor cpu1 tag_sram_1 write margin 20 22 SYS_SRAM_RW_ASSIST4 Core 0/1 SRAM Read/Write Margin Control Register 0x164 read-write n 0x0 0xFFFFFFFF RM0 Castor core_0 sram_0 read margin 0 3 RM1 Castor core_0 sram_1 read margin 8 11 RM2 Castor core_1 sram_0 read margin 16 19 RM3 Castor core_1 sram_1 read margin 24 27 WM0 Castor core_0 sram_0 write margin 4 6 WM1 Castor core_0 sram_1 write margin 12 14 WM2 Castor core_1 sram_0 write margin 20 22 WM3 Castor core_1 sram_1 write margin 28 30 SYS_SRAM_RW_ASSIST5 Core 2/3 SRAM Read/Write Margin Control Register 0x168 read-write n 0x0 0xFFFFFFFF RM0 Castor core_2 sram_0 read margin 0 3 RM1 Castor core_2 sram_1 read margin 8 11 RM2 Castor core_3 sram_0 read margin 16 19 RM3 Castor core_3 sram_1 read margin 24 27 WM0 Castor core_2 sram_0 write margin 4 6 WM1 Castor core_2 sram_1 write margin 12 14 WM2 Castor core_3 sram_0 write margin 20 22 WM3 Castor core_3 sram_1 write margin 28 30 SPCTRL Secure Privilege Control Block SPCTRL 0x50080000 0x0 0x1000 registers n AHBNSPPC0 Non-Secure Access AHB slave Peripheral Protection Control 0 0x50 read-write n 0x0 0xFFFFFFFF AHBNSPPCEXP0 Expansion 0 Non_Secure Access AHB slave Peripheral Protection Control 0x60 read-write n 0x0 0xFFFFFFFF AHBNSPPCEXP1 Expansion 1 Non_Secure Access AHB slave Peripheral Protection Control 0x64 read-write n 0x0 0xFFFFFFFF AHBNSPPCEXP2 Expansion 2 Non_Secure Access AHB slave Peripheral Protection Control 0x68 read-write n 0x0 0xFFFFFFFF AHBNSPPCEXP3 Expansion 3 Non_Secure Access AHB slave Peripheral Protection Control 0x6C read-write n 0x0 0xFFFFFFFF AHBSPPPC0 Secure Unprivileged Access AHB slave Peripheral Protection Control 0 0x90 read-only n 0x0 0xFFFFFFFF AHBSPPPCEXP0 Expansion 0 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA0 read-write n 0x0 0xFFFFFFFF AHBSPPPCEXP1 Expansion 1 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA4 read-write n 0x0 0xFFFFFFFF AHBSPPPCEXP2 Expansion 2 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA8 read-write n 0x0 0xFFFFFFFF AHBSPPPCEXP3 Expansion 3 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xAC read-write n 0x0 0xFFFFFFFF APBNSPPC0 Non-Secure Access APB slave Peripheral Protection Control 0 0x70 read-write n 0x0 0xFFFFFFFF APBNSPPC1 Non-Secure Access APB slave Peripheral Protection Control 1 0x74 read-write n 0x0 0xFFFFFFFF APBNSPPCEXP0 Expansion 0 Non_Secure Access APB slave Peripheral Protection Control 0x80 read-write n 0x0 0xFFFFFFFF APBNSPPCEXP1 Expansion 1 Non_Secure Access APB slave Peripheral Protection Control 0x84 read-write n 0x0 0xFFFFFFFF APBNSPPCEXP2 Expansion 2 Non_Secure Access APB slave Peripheral Protection Control 0x88 read-write n 0x0 0xFFFFFFFF APBNSPPCEXP3 Expansion 3 Non_Secure Access APB slave Peripheral Protection Control 0x8C read-write n 0x0 0xFFFFFFFF APBSPPPC0 Secure Unprivileged Access APB slave Peripheral Protection Control 0 0xB0 read-write n 0x0 0xFFFFFFFF APBSPPPC1 Secure Unprivileged Access APB slave Peripheral Protection Control 1 0xB4 read-write n 0x0 0xFFFFFFFF APBSPPPCEXP0 Expansion 0 Secure Unprivileged Access APB slave Peripheral Protection Control 0xC0 read-write n 0x0 0xFFFFFFFF APBSPPPCEXP1 Expansion 1 Secure Unprivileged Access APB slave Peripheral Protection Control 0xC4 read-write n 0x0 0xFFFFFFFF APBSPPPCEXP2 Expansion 2 Secure Unprivileged Access APB slave Peripheral Protection Control 0xC8 read-write n 0x0 0xFFFFFFFF APBSPPPCEXP3 Expansion 3 Secure Unprivileged Access APB slave Peripheral Protection Control 0xCC read-write n 0x0 0xFFFFFFFF BRGINTCLR Bridge Buffer Error Interrupt Clear 0x44 write-only n 0x0 0xFFFFFFFF BRGINTEN Bridge Buffer Error Interrupt Enable 0x48 read-write n 0x0 0xFFFFFFFF BRGINTSTAT Bridge Buffer Error Interrupt Status 0x40 read-only n 0x0 0xFFFFFFFF BUSWAIT Bus Access wait control after reset 0x4 read-write n 0x0 0xFFFFFFFF NSCCFG Non Secure Callable Configuration for IDAU 0x14 read-write n 0x0 0xFFFFFFFF NSMSCEXP Expansion MSC Non-Secure Configuration 0xD0 read-only n 0x0 0xFFFFFFFF SECMPCINTSTATUS Secure MPC Interrupt Status 0x1C read-only n 0x0 0xFFFFFFFF SECMSCINTCLR Secure MSC Interrupt Clear 0x34 read-write n 0x0 0xFFFFFFFF SECMSCINTEN Secure MSC Interrupt Enable 0x38 read-write n 0x0 0xFFFFFFFF SECMSCINTSTAT Secure MSC Interrupt Status 0x30 read-only n 0x0 0xFFFFFFFF SECPPCINTCLR Secure PPC Interrupt Clear 0x24 write-only n 0x0 0xFFFFFFFF SECPPCINTEN Secure PPC Interrupt Enable 0x28 read-write n 0x0 0xFFFFFFFF SECPPCINTSTAT Secure PPC Interrupt Status 0x20 read-only n 0x0 0xFFFFFFFF SECRESPCFG Security Violation Response Configuration Register 0x10 read-write n 0x0 0xFFFFFFFF SPCSECTRL Secure Privilege Controller Secure Configuration Control Register 0x0 read-write n 0x0 0xFFFFFFFF SPI0 SPI 0 SPI 0x40103000 0x0 0xFC registers n SPI_0 SPI0 Interrupt 37 SPICR Configuration Register 0x0 read-write n 0x20000 0xFFFFFFFF CPHA Clock Phase: Selects whether the SPI clock is in active or inactive phase outside the SPI word 2 3 CPOL External Clock Edge: Selects the SPI clock polarity outside SPI word 1 2 MBRD Master Baud Rate Divisor (2 to 256). The SCLK is generated base on SPI REFERENCE CLOCK or ext_clk divided by MBRD 3 6 MCSE Manual Chip Select Enable: When this bit is set, the n_ss_out[3:0] lines will be driven permanently by the encoded peripheral select value regardless of the current state of the main SPI state machine 14 15 MFGE Mode Fail Generation Enable: When this bit is set the logic generating Mode Fail is enabled 17 18 MRCS Reference Clock Select: When this bit is set the ext_clk is used, otherwise SPI REFERENCE CLOCK is used 8 9 MSC Manual Start Command: When manual start mode is enabled (see Manual Start Enable bit of Configuration Register) and TX FIFO is not empty, writing a 1 to this bit will start transmission. Writing a 0 will have no effect. It returns '0' when read 16 17 MSE Manual Start Enable: When this bit is set do not allow transmission to start until Manual Start Command (see MSC) bit is written with a '1' 15 16 MSEL Mode Select: Selects SPI controller mode (MASTER/SLAVE) 0 1 PCSL Peripheral Chip Select Lines (master mode only): When Peripheral Select Decode is set then PCSL[3:0] directly drives n_ss_out [3:0], else (PSD is written with 0) PCSL[3:0] drives n_ss_out [3:0] 10 14 PSD Peripheral Select Decode: When this bit is set allow external 4-to-16 decode (n_ss_out [3:0 = PCSL [3:0]). When Peripheral Select Decode is not set, only 1 of 4 selects n_ss_out[3:0] are active (see PCSL) 9 10 RXCLR RX FIFO Clear: Writing a 1 to this bit will clear the RX FIFO. Writing a 0 will have no effect. It returns '0' when read 19 20 SPSE Sample Point Shift Enable: When this bit is set and controller is in MASTER receiver mode then sample point of receiving data is shifted with respect to sample point of SPI protocol specification 18 19 TWS Transfer Word Size: Define size of word to be transferred. This MUST be equal to the FIFO width (FF_W), or a sub-multiple of FF_W to allow multiple word transfers per FIFO word 6 8 TXCLR TX FIFO Clear: Writing a 1 to this bit will clear the TX FIFO. Writing a '0' will have no effect. It returns 0 when read 20 21 SPIDELAY Delay Register 0x18 read-write n 0x0 0xFFFFFFFF D_AFTER Delay After 8 16 D_BTWN Delay Between 16 24 D_INIT Delay Init 0 8 D_NSS Delay NSS 24 32 SPIENR SPI Enable Register 0x14 read-write n 0x0 0xFFFFFFFF SPIE SPI Enable: When this bit is set the SPI controller is enabled, otherwise SPI is disabled. When SPI controller is disabled all output enables are inactive and all pins are set to input mode. Writing '0' disables the SPI controller once current transfer of the data word (FF_W) is complete 0 1 SPIIDR Interrupt Disable Register 0xC write-only n 0x0 0xFFFFFFFF MFD Mode Fail Disable 1 2 RFD RX FIFO Full Disable 5 6 RNED RX FIFO Not Empty Disable 4 5 ROFD RX FIFO Overflow Disable 0 1 TFD TX FIFO Full Disable 3 4 TNFD TX FIFO Not Full Disable 2 3 TUFD TX FIFO Underflow Disable 6 7 SPIIER Interrupt Enable Register 0x8 write-only n 0x0 0xFFFFFFFF MFE Mode Fail Enable 1 2 RFE RX FIFO Full Enable 5 6 RNEE RX FIFO Not Empty Enable 4 5 ROFE RX FIFO Overflow Enable 0 1 TFE TX FIFO Full Enable 3 4 TNFE TX FIFO Not Full Enable 2 3 TUFE TX FIFO Underflow Enable 6 7 SPIIMR Interrupt Mask Register 0x10 read-only n 0x0 0xFFFFFFFF MFM Mode Fail Mask 1 2 RFM RX FIFO Full Mask 5 6 RNEM RX FIFO Not Empty Mask 4 5 ROFM RX FIFO Overflow Mask 0 1 TFM TX FIFO Full Mask 3 4 TNFM TX FIFO Not Full Mask 2 3 TUFM TX FIFO Underflow Mask 6 7 SPIISR Interrupt Status Register 0x4 read-only n 0x4 0xFFFFFFFF MF Mode Fail: Indicates the voltage on pin n_ss_in is inconsistent with the SPI mode 1 2 RF RX FIFO Full (current FIFO status) 5 6 RNE RX FIFO Not Empty (current FIFO status) 4 5 ROF RX FIFO Overflow: This bit is set if an attempt is made to push the RX FIFO when it is full 0 1 TF TX FIFO Full (current FIFO status) 3 4 TNF TX FIFO Not Full (current FIFO status) 2 3 TUF TX FIFO Underflow: This bit is reset only by a system reset and cleared only when the register is read 6 7 SPIRDR Receive Data Register 0x20 read-only n 0x0 0xFFFFFFFF RDATA Receive Data: Reads the RX FIFO location indicated by the current read address and then increments the read address 0 8 SPIRTH RX FIFO Threshold Register 0x2C read-write n 0x0 0xFFFFFFFF RTRSH RX Threshold: Defines the level at which the RX FIFO not empty interrupt is generated. 0 3 SPISIC Slave Idle Count Register 0x24 read-write n 0x0 0xFFFFFFFF SICNT Slave Idle Count: SPI in slave mode detects a start only when the external SPI master serial clock (sclk_in) is stable (quiescent state) for SPI REFERENCE CLOCK cycles specified by slave idle count register or when the SPI is deselected. 0 8 SPITDR Transmit Data Register 0x1C write-only n 0x0 0xFFFFFFFF TDATA Transmit Data: Writes to the TX FIFO location indicated by its internal write address and increments the write address by pushing it 0 8 SPITTH TX FIFO Threshold Register 0x28 read-write n 0x0 0xFFFFFFFF TTRSH TX Threshold: Defines the level at which the TX FIFO not full interrupt is generated. 0 3 SPI0_Secure SPI 0 (Secure) SPI 0x50103000 0x0 0xFC registers n SPICR Configuration Register 0x0 read-write n 0x20000 0xFFFFFFFF CPHA Clock Phase: Selects whether the SPI clock is in active or inactive phase outside the SPI word 2 3 CPOL External Clock Edge: Selects the SPI clock polarity outside SPI word 1 2 MBRD Master Baud Rate Divisor (2 to 256). The SCLK is generated base on SPI REFERENCE CLOCK or ext_clk divided by MBRD 3 6 MCSE Manual Chip Select Enable: When this bit is set, the n_ss_out[3:0] lines will be driven permanently by the encoded peripheral select value regardless of the current state of the main SPI state machine 14 15 MFGE Mode Fail Generation Enable: When this bit is set the logic generating Mode Fail is enabled 17 18 MRCS Reference Clock Select: When this bit is set the ext_clk is used, otherwise SPI REFERENCE CLOCK is used 8 9 MSC Manual Start Command: When manual start mode is enabled (see Manual Start Enable bit of Configuration Register) and TX FIFO is not empty, writing a 1 to this bit will start transmission. Writing a 0 will have no effect. It returns '0' when read 16 17 MSE Manual Start Enable: When this bit is set do not allow transmission to start until Manual Start Command (see MSC) bit is written with a '1' 15 16 MSEL Mode Select: Selects SPI controller mode (MASTER/SLAVE) 0 1 PCSL Peripheral Chip Select Lines (master mode only): When Peripheral Select Decode is set then PCSL[3:0] directly drives n_ss_out [3:0], else (PSD is written with 0) PCSL[3:0] drives n_ss_out [3:0] 10 14 PSD Peripheral Select Decode: When this bit is set allow external 4-to-16 decode (n_ss_out [3:0 = PCSL [3:0]). When Peripheral Select Decode is not set, only 1 of 4 selects n_ss_out[3:0] are active (see PCSL) 9 10 RXCLR RX FIFO Clear: Writing a 1 to this bit will clear the RX FIFO. Writing a 0 will have no effect. It returns '0' when read 19 20 SPSE Sample Point Shift Enable: When this bit is set and controller is in MASTER receiver mode then sample point of receiving data is shifted with respect to sample point of SPI protocol specification 18 19 TWS Transfer Word Size: Define size of word to be transferred. This MUST be equal to the FIFO width (FF_W), or a sub-multiple of FF_W to allow multiple word transfers per FIFO word 6 8 TXCLR TX FIFO Clear: Writing a 1 to this bit will clear the TX FIFO. Writing a '0' will have no effect. It returns 0 when read 20 21 SPIDELAY Delay Register 0x18 read-write n 0x0 0xFFFFFFFF D_AFTER Delay After 8 16 D_BTWN Delay Between 16 24 D_INIT Delay Init 0 8 D_NSS Delay NSS 24 32 SPIENR SPI Enable Register 0x14 read-write n 0x0 0xFFFFFFFF SPIE SPI Enable: When this bit is set the SPI controller is enabled, otherwise SPI is disabled. When SPI controller is disabled all output enables are inactive and all pins are set to input mode. Writing '0' disables the SPI controller once current transfer of the data word (FF_W) is complete 0 1 SPIIDR Interrupt Disable Register 0xC write-only n 0x0 0xFFFFFFFF MFD Mode Fail Disable 1 2 RFD RX FIFO Full Disable 5 6 RNED RX FIFO Not Empty Disable 4 5 ROFD RX FIFO Overflow Disable 0 1 TFD TX FIFO Full Disable 3 4 TNFD TX FIFO Not Full Disable 2 3 TUFD TX FIFO Underflow Disable 6 7 SPIIER Interrupt Enable Register 0x8 write-only n 0x0 0xFFFFFFFF MFE Mode Fail Enable 1 2 RFE RX FIFO Full Enable 5 6 RNEE RX FIFO Not Empty Enable 4 5 ROFE RX FIFO Overflow Enable 0 1 TFE TX FIFO Full Enable 3 4 TNFE TX FIFO Not Full Enable 2 3 TUFE TX FIFO Underflow Enable 6 7 SPIIMR Interrupt Mask Register 0x10 read-only n 0x0 0xFFFFFFFF MFM Mode Fail Mask 1 2 RFM RX FIFO Full Mask 5 6 RNEM RX FIFO Not Empty Mask 4 5 ROFM RX FIFO Overflow Mask 0 1 TFM TX FIFO Full Mask 3 4 TNFM TX FIFO Not Full Mask 2 3 TUFM TX FIFO Underflow Mask 6 7 SPIISR Interrupt Status Register 0x4 read-only n 0x4 0xFFFFFFFF MF Mode Fail: Indicates the voltage on pin n_ss_in is inconsistent with the SPI mode 1 2 RF RX FIFO Full (current FIFO status) 5 6 RNE RX FIFO Not Empty (current FIFO status) 4 5 ROF RX FIFO Overflow: This bit is set if an attempt is made to push the RX FIFO when it is full 0 1 TF TX FIFO Full (current FIFO status) 3 4 TNF TX FIFO Not Full (current FIFO status) 2 3 TUF TX FIFO Underflow: This bit is reset only by a system reset and cleared only when the register is read 6 7 SPIRDR Receive Data Register 0x20 read-only n 0x0 0xFFFFFFFF RDATA Receive Data: Reads the RX FIFO location indicated by the current read address and then increments the read address 0 8 SPIRTH RX FIFO Threshold Register 0x2C read-write n 0x0 0xFFFFFFFF RTRSH RX Threshold: Defines the level at which the RX FIFO not empty interrupt is generated. 0 3 SPISIC Slave Idle Count Register 0x24 read-write n 0x0 0xFFFFFFFF SICNT Slave Idle Count: SPI in slave mode detects a start only when the external SPI master serial clock (sclk_in) is stable (quiescent state) for SPI REFERENCE CLOCK cycles specified by slave idle count register or when the SPI is deselected. 0 8 SPITDR Transmit Data Register 0x1C write-only n 0x0 0xFFFFFFFF TDATA Transmit Data: Writes to the TX FIFO location indicated by its internal write address and increments the write address by pushing it 0 8 SPITTH TX FIFO Threshold Register 0x28 read-write n 0x0 0xFFFFFFFF TTRSH TX Threshold: Defines the level at which the TX FIFO not full interrupt is generated. 0 3 SRAM0_MPC Memory Protection Controller 0 MPC 0x50083000 0x0 0x1000 registers n MPC MPC Combined 9 BLK_CFG Block Configuration 0x14 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index Register 0x10 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 32 bit[3_0] Block size 0 4 CTRL MPC Control Register 0x0 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 32 bit[4] Security error response configuration 4 5 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 7 bit[7] Data interface gating acknowledge (RO) 7 8 bit[8] Auto-increment 8 9 INT_CLEAR Interrupt clear 0x24 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 17 bit[17] cfg_ns 17 18 INT_SET Interrupt set. Debug purpose only 0x34 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 SRAM0_PPU SRAM0 Power Policy Unit PPU 0x5002A000 0x0 0x1000 registers n AIDR Architecture Identification Register 0xFCC read-only n 0x0 0xFFFFFFFF AIMR Additional Interrupt Mask Register 0x34 read-write n 0x0 0xFFFFFFFF AISR Additional Interrupt Status Register 0x3C read-write n 0x0 0xFFFFFFFF DCDR0 Device Control Delay Configuration Register 0 0x170 read-write n 0x0 0xFFFFFFFF DCDR1 Device Control Delay Configuration Register 1 0x174 read-write n 0x0 0xFFFFFFFF DISR Device Interface Input Current Status Register 0x10 read-only n 0x0 0xFFFFFFFF EDTR0 Power Mode Entry Delay Register 0 0x160 read-write n 0x0 0xFFFFFFFF EDTR1 Power Mode Entry Delay Register 1 0x164 read-write n 0x0 0xFFFFFFFF FULRR Full Retention RAM Configuration Register 0x54 read-write n 0x0 0xFFFFFFFF FUNRR Functional Retention RAM Configuration Register 0x50 read-write n 0x0 0xFFFFFFFF IDR0 PPU Identification Register 0 0xFB0 read-only n 0x0 0xFFFFFFFF IDR1 PPU Identification Register 1 0xFB4 read-only n 0x0 0xFFFFFFFF IESR Input Edge Sensitivity Register 0x40 read-write n 0x0 0xFFFFFFFF IIDR Implementation Identification Register 0xFC8 read-only n 0x0 0xFFFFFFFF IMR Interrupt Mask Register 0x30 read-write n 0x0 0xFFFFFFFF ISR Interrupt Status Register 0x38 read-write n 0x0 0xFFFFFFFF MEMRR Memory Retention RAM Configuration Register 0x58 read-write n 0x0 0xFFFFFFFF MISR Miscellaneous Input Current Status Register 0x14 read-only n 0x0 0xFFFFFFFF OPSR Operating Mode Active Edge Sensitivity Register 0x44 read-write n 0x0 0xFFFFFFFF PMER Power Mode Emulation Register 0x4 read-write n 0x0 0xFFFFFFFF PTCR Power Mode Transition Configuration Register 0x24 read-write n 0x0 0xFFFFFFFF PWCR Power Configuration Register 0x20 read-write n 0x0 0xFFFFFFFF PWPR Power Policy Register 0x0 read-write n 0x0 0xFFFFFFFF PWSR Power Status Register 0x8 read-only n 0x0 0xFFFFFFFF STSR Stored Status Register 0x18 read-only n 0x0 0xFFFFFFFF UNLK Unlock Register 0x1C read-write n 0x0 0xFFFFFFFF SRAM1_MPC SRAM 1 Memory Protection Controller MPC 0x50084000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index Register 0x10 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 32 bit[3_0] Block size 0 4 CTRL MPC Control Register 0x0 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 32 bit[4] Security error response configuration 4 5 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 7 bit[7] Data interface gating acknowledge (RO) 7 8 bit[8] Auto-increment 8 9 INT_CLEAR Interrupt clear 0x24 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 17 bit[17] cfg_ns 17 18 INT_SET Interrupt set. Debug purpose only 0x34 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 SRAM1_PPU SRAM1 Power Policy Unit PPU 0x5002B000 0x0 0x1000 registers n AIDR Architecture Identification Register 0xFCC read-only n 0x0 0xFFFFFFFF AIMR Additional Interrupt Mask Register 0x34 read-write n 0x0 0xFFFFFFFF AISR Additional Interrupt Status Register 0x3C read-write n 0x0 0xFFFFFFFF DCDR0 Device Control Delay Configuration Register 0 0x170 read-write n 0x0 0xFFFFFFFF DCDR1 Device Control Delay Configuration Register 1 0x174 read-write n 0x0 0xFFFFFFFF DISR Device Interface Input Current Status Register 0x10 read-only n 0x0 0xFFFFFFFF EDTR0 Power Mode Entry Delay Register 0 0x160 read-write n 0x0 0xFFFFFFFF EDTR1 Power Mode Entry Delay Register 1 0x164 read-write n 0x0 0xFFFFFFFF FULRR Full Retention RAM Configuration Register 0x54 read-write n 0x0 0xFFFFFFFF FUNRR Functional Retention RAM Configuration Register 0x50 read-write n 0x0 0xFFFFFFFF IDR0 PPU Identification Register 0 0xFB0 read-only n 0x0 0xFFFFFFFF IDR1 PPU Identification Register 1 0xFB4 read-only n 0x0 0xFFFFFFFF IESR Input Edge Sensitivity Register 0x40 read-write n 0x0 0xFFFFFFFF IIDR Implementation Identification Register 0xFC8 read-only n 0x0 0xFFFFFFFF IMR Interrupt Mask Register 0x30 read-write n 0x0 0xFFFFFFFF ISR Interrupt Status Register 0x38 read-write n 0x0 0xFFFFFFFF MEMRR Memory Retention RAM Configuration Register 0x58 read-write n 0x0 0xFFFFFFFF MISR Miscellaneous Input Current Status Register 0x14 read-only n 0x0 0xFFFFFFFF OPSR Operating Mode Active Edge Sensitivity Register 0x44 read-write n 0x0 0xFFFFFFFF PMER Power Mode Emulation Register 0x4 read-write n 0x0 0xFFFFFFFF PTCR Power Mode Transition Configuration Register 0x24 read-write n 0x0 0xFFFFFFFF PWCR Power Configuration Register 0x20 read-write n 0x0 0xFFFFFFFF PWPR Power Policy Register 0x0 read-write n 0x0 0xFFFFFFFF PWSR Power Status Register 0x8 read-only n 0x0 0xFFFFFFFF STSR Stored Status Register 0x18 read-only n 0x0 0xFFFFFFFF UNLK Unlock Register 0x1C read-write n 0x0 0xFFFFFFFF SRAM2_MPC SRAM 2 Memory Protection Controller MPC 0x50085000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index Register 0x10 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 32 bit[3_0] Block size 0 4 CTRL MPC Control Register 0x0 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 32 bit[4] Security error response configuration 4 5 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 7 bit[7] Data interface gating acknowledge (RO) 7 8 bit[8] Auto-increment 8 9 INT_CLEAR Interrupt clear 0x24 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 17 bit[17] cfg_ns 17 18 INT_SET Interrupt set. Debug purpose only 0x34 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 SRAM2_PPU SRAM2 Power Policy Unit PPU 0x5002C000 0x0 0x1000 registers n AIDR Architecture Identification Register 0xFCC read-only n 0x0 0xFFFFFFFF AIMR Additional Interrupt Mask Register 0x34 read-write n 0x0 0xFFFFFFFF AISR Additional Interrupt Status Register 0x3C read-write n 0x0 0xFFFFFFFF DCDR0 Device Control Delay Configuration Register 0 0x170 read-write n 0x0 0xFFFFFFFF DCDR1 Device Control Delay Configuration Register 1 0x174 read-write n 0x0 0xFFFFFFFF DISR Device Interface Input Current Status Register 0x10 read-only n 0x0 0xFFFFFFFF EDTR0 Power Mode Entry Delay Register 0 0x160 read-write n 0x0 0xFFFFFFFF EDTR1 Power Mode Entry Delay Register 1 0x164 read-write n 0x0 0xFFFFFFFF FULRR Full Retention RAM Configuration Register 0x54 read-write n 0x0 0xFFFFFFFF FUNRR Functional Retention RAM Configuration Register 0x50 read-write n 0x0 0xFFFFFFFF IDR0 PPU Identification Register 0 0xFB0 read-only n 0x0 0xFFFFFFFF IDR1 PPU Identification Register 1 0xFB4 read-only n 0x0 0xFFFFFFFF IESR Input Edge Sensitivity Register 0x40 read-write n 0x0 0xFFFFFFFF IIDR Implementation Identification Register 0xFC8 read-only n 0x0 0xFFFFFFFF IMR Interrupt Mask Register 0x30 read-write n 0x0 0xFFFFFFFF ISR Interrupt Status Register 0x38 read-write n 0x0 0xFFFFFFFF MEMRR Memory Retention RAM Configuration Register 0x58 read-write n 0x0 0xFFFFFFFF MISR Miscellaneous Input Current Status Register 0x14 read-only n 0x0 0xFFFFFFFF OPSR Operating Mode Active Edge Sensitivity Register 0x44 read-write n 0x0 0xFFFFFFFF PMER Power Mode Emulation Register 0x4 read-write n 0x0 0xFFFFFFFF PTCR Power Mode Transition Configuration Register 0x24 read-write n 0x0 0xFFFFFFFF PWCR Power Configuration Register 0x20 read-write n 0x0 0xFFFFFFFF PWPR Power Policy Register 0x0 read-write n 0x0 0xFFFFFFFF PWSR Power Status Register 0x8 read-only n 0x0 0xFFFFFFFF STSR Stored Status Register 0x18 read-only n 0x0 0xFFFFFFFF UNLK Unlock Register 0x1C read-write n 0x0 0xFFFFFFFF SRAM3_MPC SRAM 3 Memory Protection Controller MPC 0x50086000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index Register 0x10 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 32 bit[3_0] Block size 0 4 CTRL MPC Control Register 0x0 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 32 bit[4] Security error response configuration 4 5 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 7 bit[7] Data interface gating acknowledge (RO) 7 8 bit[8] Auto-increment 8 9 INT_CLEAR Interrupt clear 0x24 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 17 bit[17] cfg_ns 17 18 INT_SET Interrupt set. Debug purpose only 0x34 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 SRAM3_PPU SRAM3 Power Policy Unit PPU 0x5002D000 0x0 0x1000 registers n AIDR Architecture Identification Register 0xFCC read-only n 0x0 0xFFFFFFFF AIMR Additional Interrupt Mask Register 0x34 read-write n 0x0 0xFFFFFFFF AISR Additional Interrupt Status Register 0x3C read-write n 0x0 0xFFFFFFFF DCDR0 Device Control Delay Configuration Register 0 0x170 read-write n 0x0 0xFFFFFFFF DCDR1 Device Control Delay Configuration Register 1 0x174 read-write n 0x0 0xFFFFFFFF DISR Device Interface Input Current Status Register 0x10 read-only n 0x0 0xFFFFFFFF EDTR0 Power Mode Entry Delay Register 0 0x160 read-write n 0x0 0xFFFFFFFF EDTR1 Power Mode Entry Delay Register 1 0x164 read-write n 0x0 0xFFFFFFFF FULRR Full Retention RAM Configuration Register 0x54 read-write n 0x0 0xFFFFFFFF FUNRR Functional Retention RAM Configuration Register 0x50 read-write n 0x0 0xFFFFFFFF IDR0 PPU Identification Register 0 0xFB0 read-only n 0x0 0xFFFFFFFF IDR1 PPU Identification Register 1 0xFB4 read-only n 0x0 0xFFFFFFFF IESR Input Edge Sensitivity Register 0x40 read-write n 0x0 0xFFFFFFFF IIDR Implementation Identification Register 0xFC8 read-only n 0x0 0xFFFFFFFF IMR Interrupt Mask Register 0x30 read-write n 0x0 0xFFFFFFFF ISR Interrupt Status Register 0x38 read-write n 0x0 0xFFFFFFFF MEMRR Memory Retention RAM Configuration Register 0x58 read-write n 0x0 0xFFFFFFFF MISR Miscellaneous Input Current Status Register 0x14 read-only n 0x0 0xFFFFFFFF OPSR Operating Mode Active Edge Sensitivity Register 0x44 read-write n 0x0 0xFFFFFFFF PMER Power Mode Emulation Register 0x4 read-write n 0x0 0xFFFFFFFF PTCR Power Mode Transition Configuration Register 0x24 read-write n 0x0 0xFFFFFFFF PWCR Power Configuration Register 0x20 read-write n 0x0 0xFFFFFFFF PWPR Power Policy Register 0x0 read-write n 0x0 0xFFFFFFFF PWSR Power Status Register 0x8 read-only n 0x0 0xFFFFFFFF STSR Stored Status Register 0x18 read-only n 0x0 0xFFFFFFFF UNLK Unlock Register 0x1C read-write n 0x0 0xFFFFFFFF SYSCTRL System Control (Secure) SYSCTRL 0x50021000 0x0 0x1000 registers n CLOCK_FORCE Clock Forces 0x18 read-write n 0x0 0xFFFFFFFF CPUWAIT CPU Boot wait control after reset 0x118 read-write n 0x0 0xFFFFFFFF EWCTRL External Wakeup Control 0x124 read-write n 0x0 0xFFFFFFFF FCLK_DIV Fast Clock Divider Configuration Register 0x10 read-write n 0x0 0xFFFFFFFF GRETREG General Purpose Retention Register 0x10C read-write n 0x0 0xFFFFFFFF INITSVTOR0 Initial Secure Reset Vector Register For CPU 0 0x110 read-write n 0x0 0xFFFFFFFF INITSVTOR1 Initial Secure Reset Vector Register For CPU 1 0x114 read-write n 0x0 0xFFFFFFFF NMI_ENABLE NMI Enable Register 0x11C read-write n 0x1 0xFFFFFFFF PDCM_PD_SRAM0_SENSE Power Control Dependency Matrix PD_SRAM0 Power Domain Sensitivity 0x20C read-write n 0x0 0xFFFFFFFF PDCM_PD_SRAM1_SENSE Power Control Dependency Matrix PD_SRAM1 Power Domain Sensitivity 0x210 read-write n 0x0 0xFFFFFFFF PDCM_PD_SRAM2_SENSE Power Control Dependency Matrix PD_SRAM2 Power Domain Sensitivity 0x214 read-write n 0x0 0xFFFFFFFF PDCM_PD_SRAM3_SENSE Power Control Dependency Matrix PD_SRAM3 Power Domain Sensitivity 0x218 read-write n 0x0 0xFFFFFFFF PDCM_PD_SYS_SENSE Power Control Dependency Matrix PD_SYS Power Domain Sensitivity 0x200 read-write n 0x7F 0xFFFFFFFF RESET_MASK Reset MASK 0x104 read-write n 0x30 0xFFFFFFFF RESET_SYNDROME Reset syndrome 0x100 read-write n 0x1 0xFFFFFFFF SCSECCTRL System Control Security Control Register 0xC read-write n 0x0 0xFFFFFFFF SECDBGCLR Secure Debug Configuration Clear Register 0x8 write-only n 0x0 0xFFFFFFFF SECDBGSET Secure Debug Configuration Set Register 0x4 write-only n 0x0 0xFFFFFFFF SECDBGSTAT Secure Debug Configuration Status Register 0x0 read-only n 0x0 0xFFFFFFFF SWRESET Software Reset 0x108 write-only n 0x0 0xFFFFFFFF SYSCLK_DIV System Clock Divider Configuration Register 0x14 read-write n 0x0 0xFFFFFFFF WICCTRL CPU WIC Request and Acknowledgement 0x120 read-write n 0x0 0xFFFFFFFF SYS_PPU SYS Power Policy Unit PPU 0x50022000 0x0 0x1000 registers n AIDR Architecture Identification Register 0xFCC read-only n 0x0 0xFFFFFFFF AIMR Additional Interrupt Mask Register 0x34 read-write n 0x0 0xFFFFFFFF AISR Additional Interrupt Status Register 0x3C read-write n 0x0 0xFFFFFFFF DCDR0 Device Control Delay Configuration Register 0 0x170 read-write n 0x0 0xFFFFFFFF DCDR1 Device Control Delay Configuration Register 1 0x174 read-write n 0x0 0xFFFFFFFF DISR Device Interface Input Current Status Register 0x10 read-only n 0x0 0xFFFFFFFF EDTR0 Power Mode Entry Delay Register 0 0x160 read-write n 0x0 0xFFFFFFFF EDTR1 Power Mode Entry Delay Register 1 0x164 read-write n 0x0 0xFFFFFFFF FULRR Full Retention RAM Configuration Register 0x54 read-write n 0x0 0xFFFFFFFF FUNRR Functional Retention RAM Configuration Register 0x50 read-write n 0x0 0xFFFFFFFF IDR0 PPU Identification Register 0 0xFB0 read-only n 0x0 0xFFFFFFFF IDR1 PPU Identification Register 1 0xFB4 read-only n 0x0 0xFFFFFFFF IESR Input Edge Sensitivity Register 0x40 read-write n 0x0 0xFFFFFFFF IIDR Implementation Identification Register 0xFC8 read-only n 0x0 0xFFFFFFFF IMR Interrupt Mask Register 0x30 read-write n 0x0 0xFFFFFFFF ISR Interrupt Status Register 0x38 read-write n 0x0 0xFFFFFFFF MEMRR Memory Retention RAM Configuration Register 0x58 read-write n 0x0 0xFFFFFFFF MISR Miscellaneous Input Current Status Register 0x14 read-only n 0x0 0xFFFFFFFF OPSR Operating Mode Active Edge Sensitivity Register 0x44 read-write n 0x0 0xFFFFFFFF PMER Power Mode Emulation Register 0x4 read-write n 0x0 0xFFFFFFFF PTCR Power Mode Transition Configuration Register 0x24 read-write n 0x0 0xFFFFFFFF PWCR Power Configuration Register 0x20 read-write n 0x0 0xFFFFFFFF PWPR Power Policy Register 0x0 read-write n 0x0 0xFFFFFFFF PWSR Power Status Register 0x8 read-only n 0x0 0xFFFFFFFF STSR Stored Status Register 0x18 read-only n 0x0 0xFFFFFFFF UNLK Unlock Register 0x1C read-write n 0x0 0xFFFFFFFF TIMER0 Timer 0 Timer 0x40000000 0x0 0x10 registers n TIMER0 Timer 0 3 CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 EXTCLK External Clock Enable 2 3 EXTIN External Input as Enable 1 2 INTEN Interrupt Enable 3 4 INTCLEAR Timer Interrupt clear Register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF oneToClear INTSTATUS Timer Interrupt status Register 0xC read-only n 0x0 0xFFFFFFFF RELOAD Counter Reload Value 0x8 read-write n 0x0 0xFFFFFFFF VALUE Current Timer Counter Value 0x4 read-write n 0x0 0xFFFFFFFF TIMER0_Secure Timer 0 (Secure) Timer 0x50000000 0x0 0x10 registers n CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 EXTCLK External Clock Enable 2 3 EXTIN External Input as Enable 1 2 INTEN Interrupt Enable 3 4 INTCLEAR Timer Interrupt clear Register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF oneToClear INTSTATUS Timer Interrupt status Register 0xC read-only n 0x0 0xFFFFFFFF RELOAD Counter Reload Value 0x8 read-write n 0x0 0xFFFFFFFF VALUE Current Timer Counter Value 0x4 read-write n 0x0 0xFFFFFFFF TIMER1 Timer 1 Timer 0x40001000 0x0 0x10 registers n TIMER1 Timer 1 4 CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 EXTCLK External Clock Enable 2 3 EXTIN External Input as Enable 1 2 INTEN Interrupt Enable 3 4 INTCLEAR Timer Interrupt clear Register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF oneToClear INTSTATUS Timer Interrupt status Register 0xC read-only n 0x0 0xFFFFFFFF RELOAD Counter Reload Value 0x8 read-write n 0x0 0xFFFFFFFF VALUE Current Timer Counter Value 0x4 read-write n 0x0 0xFFFFFFFF TIMER1_Secure Timer 1 (Secure) Power Manager 0x50001000 0x0 0x40 registers n FLAGS Power Sequencer Flags 0x20 read-write n 0x0 0xFFFFFFFF pwr_boot_fail Boot Fail event detected flag 3 4 read-write oneToClear pwr_first_boot Initial Boot event detected flag 0 1 read-only pwr_flash_discharge Flash Discharged During Powerfail event detected flag 4 5 read-write oneToClear pwr_iowakeup GPIO Wakeup event detected flag 5 6 read-write oneToClear pwr_por18z_fail_latch POR18 and POR18_bg have been tripped 11 12 read-write oneToClear pwr_power_fail Power Fail event detected flag 2 3 read-write oneToClear pwr_sys_reboot Firmware Reset event detected flag 1 2 read-only pwr_tvdd12_bad Retention Regulator POR Tripped event detected flag 18 19 read-write oneToClear pwr_tvdd12_rst_bad TVDD12 Comparator Tripped event detected flag 10 11 read-write oneToClear pwr_usb_plug_wakeup USB Power Connect Wakeup event detected flag 16 17 read-write oneToClear pwr_usb_remove_wakeup USB Power Remove Wakeup event detected flag 17 18 read-write oneToClear pwr_vdd12_rst_bad VDD12_SW Comparator Tripped event detected flag 6 7 read-write oneToClear pwr_vdd18_rst_bad VDD18_SW Comparator Tripped event detected flag 7 8 read-write oneToClear pwr_vddb_rst_bad VDDB Comparator Tripped event detected flag 9 10 read-write oneToClear pwr_vrtc_rst_bad VRTC Comparator Tripped event detected flag 8 9 read-write oneToClear rtc_cmpr0 RTC Comparator 0 Match event detected flag 12 13 read-only rtc_cmpr1 RTC Comparator 1 Match event detected flag 13 14 read-only rtc_prescale_cmp RTC Prescale Comparator Match event detected flag 14 15 read-only rtc_rollover RTC Rollover event detected flag 15 16 read-only MSK_FLAGS Power Sequencer Flags Mask Register 0x24 read-write n 0x0 0xFFFFFFFF pwr_boot_fail Mask for previous boot fail detect 3 4 read-write pwr_flash_discharge Mask for flash discharge event 4 5 read-write pwr_iowakeup Mask for GPIO wakeup event detect 5 6 read-write pwr_por18z_fail_latch Mask for POR18 powerfail event 11 12 read-write pwr_power_fail Mask for previous power fail detect 2 3 read-write pwr_sys_reboot Mask for system reboot detect 1 2 read-write pwr_tvdd12_bad Mask for TVDD12 power fail event 18 19 read-write pwr_tvdd12_rst_bad Mask for TVDD12 rst event 10 11 read-write pwr_usb_plug_wakeup Mask for USB plug connect event 16 17 read-write pwr_usb_remove_wakeup Mask for USB plug disconnect event 17 18 read-write pwr_vdd12_rst_bad Mask for VDD12 rst event 6 7 read-write pwr_vdd18_rst_bad Mask for VDD18 rst event 7 8 read-write pwr_vddb_rst_bad Mask for VDDB rst event 9 10 read-write pwr_vrtc_rst_bad Mask for VRTC rst event 8 9 read-write rtc_cmpr0 Mask for RTC compare 0 event 12 13 read-write rtc_cmpr1 Mask for RTC compare 1 event 13 14 read-write rtc_prescale_cmp Mask for RTC prescale compare event 14 15 read-write rtc_rollover Mask for RTC rollover event 15 16 read-write REG0 Power Sequencer Control Register 0 0x0 read-write n 0x0 0xFFFFFFFF pwr_first_boot Wake on First Boot 1 2 read-write pwr_flashen_run Enable Flash Operation during Run Mode 3 4 read-write pwr_flashen_slp Enable Flash Operation during Sleep Mode 4 5 read-write pwr_lp1 Shutdown Power Mode Select 0 1 read-write pwr_nren_run Enable Nano Oscillator in Run Mode 9 10 read-write pwr_nren_slp Enable Nano Oscillator in Sleep Mode 10 11 read-write pwr_retregen_run Enable Retention Regulator Operation during Run Mode 5 6 read-write pwr_retregen_slp Enable Retention Regulator Operation during Sleep Mode 6 7 read-write pwr_roen_run Enable 96MHz System Relaxation Oscillator in Run Mode 7 8 read-write pwr_roen_slp Enable 96MHz System Relaxation Oscillator in Sleep Mode 8 9 read-write pwr_rtcen_run Enable Real Time Clock Operation during Run Mode 11 12 read-write pwr_rtcen_slp Enable Real Time Clock Operation during Sleep Mode 12 13 read-write pwr_svm12en_run Enable VDD12_SW SVM operation during Run Mode 13 14 read-write pwr_svm18en_run Enable VDD18_SW SVM operation during Run Mode 15 16 read-write pwr_svmrtcen_run Enable VRTC SVM operation during Run Mode 17 18 read-write pwr_svmtvdd12en_run Enable TVDD12 SVM operation during Run Mode 21 22 read-write pwr_svm_vddb_run Enable VDDB SVM operation during Run Mode 19 20 read-write pwr_sys_reboot Firmware System Reboot Request 2 3 write-only pwr_tvdd12_swen_run Enable TVDD12 switching during Run Mode 27 28 read-write pwr_tvdd12_swen_slp Enable TVDD12 switching during Sleep Mode 28 29 read-write pwr_vdd12_swen_run Enable VDD12 switching during Run Mode 23 24 read-write pwr_vdd12_swen_slp Enable VDD12 switching during Sleep Mode 24 25 read-write pwr_vdd18_swen_run Enable VDD18 switching during Run Mode 25 26 read-write pwr_vdd18_swen_slp Enable VDD18 switching during Sleep Mode 26 27 read-write REG1 Power Sequencer Control Register 1 0x4 read-write n 0x0 0xFFFFFFFF pwr_clr_io_cfg_latch Clear all GPIO Configuration Latches 1 2 read-write pwr_clr_io_event_latch Clear all GPIO Event Seen Latches 0 1 read-write pwr_discharge_en Enable Flash Discharge During Powerfail Event 3 4 read-write pwr_mbus_gate Freeze GPIO MBus State 2 3 read-write pwr_tvdd12_well TVDD12 Well Switch 4 5 read-write REG2 Power Sequencer Control Register 2 0x8 read-write n 0x0 0xFFFFFFFF pwr_tvdd12_hyst TVDD12 Comparator Hysteresis Setting 8 10 read-write pwr_vdd12_hyst VDD12_SW Comparator Hysteresis Setting 0 2 read-write pwr_vdd18_hyst VDD18_SW Comparator Hysteresis Setting 2 4 read-write pwr_vddb_hyst VDDB Comparator Hysteresis Setting 6 8 read-write pwr_vrtc_hyst VRTC Comparator Hysteresis Setting 4 6 read-write REG3 Power Sequencer Control Register 3 0xC read-write n 0x0 0xFFFFFFFF pwr_failsel Timeout before rebooting during PowerFail/BootFail events. 10 13 read-write pwr_fltrrosel Window of time power must be valid before entering Run mode. 3 6 read-write pwr_rosel Relaxation Oscillator Stable Timeout 0 3 read-write pwr_ro_clk_mux Relaxation Clock Mux 8 10 read-write pwr_svm_clk_mux SVM Clock Mux 6 8 read-write REG4 Power Sequencer Control Register 4 (Internal Test Only) 0x10 read-write n 0x0 0xFFFFFFFF pwr_ext_clk_in_en Internal Use Only 6 7 read-write pwr_nr_clk_gate_en Internal Use Only 5 6 read-write pwr_pseq_32k_en Internal Use Only 7 8 read-write pwr_ro_tstclk_en Internal Use Only 4 5 read-write pwr_tm_fast_timers Internal Use Only 1 2 read-write pwr_tm_ps_2_gpio Internal Use Only 0 1 read-write pwr_usb_dis_comp Internal Use Only 3 4 read-write REG5 Power Sequencer Control Register 5 (Trim 0) 0x14 read-write n 0x0 0xFFFFFFFF pwr_rtc_trim Real Time Clock trim setting 21 25 read-write pwr_trim_bias Power Manager Bias Current trim setting 9 15 read-write pwr_trim_retreg Retention Regulator trim setting 15 21 read-write pwr_trim_svm_bg Power Manager Bandgap trim setting 0 9 read-write REG6 Power Sequencer Control Register 6 (Trim 1) 0x18 read-write n 0x0 0xFFFFFFFF pwr_trim_crypto_osc Crypto Oscillator trim setting 20 29 read-write pwr_trim_osc_vref Relaxation Oscillator trim setting 11 20 read-write pwr_trim_usb_bias USB Bias Current trim setting 0 3 read-write pwr_trim_usb_dm_res USB Data Minus Slew Rate trim setting 7 11 read-write pwr_trim_usb_pm_res USB Data Plus Slew Rate trim setting 3 7 read-write REG7 Power Sequencer Control Register 7 0x1C read-write n 0x0 0xFFFFFFFF pwr_flash_pd_lookahead Flash Powerdown Lookahead Flag 0 1 read-only UART0 UART 0 UART 0x40101000 0x0 0x4C registers n UART_0 UART0 Interrupt 44 UARTCR Control Register 0x30 read-write n 0x300 0xFFFFFFFF CTSEn CTS hardware flow control enable 15 16 Disable CTS hardware flow control is disabled 0 Enable CTS hardware flow control is enabled 1 DTR Data transmit ready 10 11 LBE Loop back enable 7 8 Disable Loop back mode is disabled 0 Enable Loop back mode is enabled 1 Out1 Complement of the UART Out1 12 13 Out2 Complement of the UART Out2 13 14 RTS Request to send 11 12 RTSEn RTS hardware flow control enable 14 15 Disable RTS hardware flow control is disabled 0 Enable RTS hardware flow control is enabled 1 RXE Receive enable 9 10 Disable Reception is disabled 0 Enable Reception is enabled 1 SIREN SIR enable 1 2 Disable SIR is disabled 0 Enable SIR is enabled 1 SIRLP IrDA SIR low power mode 2 3 Disable SIR low power mode is disabled 0 Enable SIR low power mode is enabled 1 TXE Transmit enable 8 9 Disable Transmission is disabled 0 Enable Transmission is enabled 1 UARTEN UART enable 0 1 Disable UART is disabled 0 Enable UART is enabled 1 UARTDMACR DMA control Register 0x48 read-write n 0x0 0xFFFFFFFF DMAONERR DMA on error 2 3 Disable DMA receive request outputs are enabled when the UART error interrupt is asserted 0 Enable DMA receive request outputs are disabled when the UART error interrupt is asserted 1 RXDMAE Receive DMA enable 0 1 Disable Receive DMA is disabled 0 Enable Receive DMA is enabled 1 TXDMAE Transmit DMA enable 1 1 Disable Transmit DMA is disabled 0 Enable Transmit DMA is enabled 1 UARTDR Data Register 0x0 read-write n 0x0 0xFFFFFFFF BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 10 11 Data Receive/Transmit data 0 8 FE Framing error: Indicates the received character did not had a valid stop bit 8 9 OE Overrun error: Indicates if data is received and the receive FIFO is already full 11 12 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 9 10 UARTFBRD Fractional baud rate Register 0x28 read-write n 0x0 0xFFFFFFFF BAUD_DIVINT The integer baud rate divisor 0 6 UARTFR Flag Register 0x18 read-only n 0x0 0xFFFFFFFF BUSY UART busy 3 4 CTS Clear to send 0 1 DCD Data carrier detect 2 3 DSR Data set ready 1 2 RI Ring indicator 8 9 RXFE Receive FIFO empty 4 5 RXFF Receive FIFO full 6 7 TXFE Transmit FIFO empty 7 8 TXFF Transmit FIFO full 5 6 UARTIBRD Integer baud rate Register 0x24 read-write n 0x0 0xFFFFFFFF BAUD_DIVINT The integer baud rate divisor 0 16 UARTICR Interrupt clear Register 0x44 write-only n 0x0 0xFFFFFFFF BEIC Break error interrupt clear, write 1 to clear, write 0 has no effect 9 1 CTSMIC nUARTCTS modem interrupt clear, write 1 to clear, write 0 has no effect 1 1 DCDMIC nUARTDCD modem interrupt clear, write 1 to clear, write 0 has no effect 2 1 DSRIC nUARTDSR modem interrupt clear, write 1 to clear, write 0 has no effect 3 1 FEIC Framing error interrupt clear, write 1 to clear, write 0 has no effect 7 1 OEIC Overrun error interrupt clear, write 1 to clear, write 0 has no effect 10 1 PEIC Parity error interrupt clear, write 1 to clear, write 0 has no effect 8 1 RIMIC nUARTRI modem interrupt clear, write 1 to clear, write 0 has no effect 0 1 RTIC Receive timeout interrupt clear, write 1 to clear, write 0 has no effect 6 1 RXIC Receive interrupt clear, write 1 to clear, write 0 has no effect 4 1 TXIC Transmit interrupt clear, write 1 to clear, write 0 has no effect 5 1 UARTIFLS Interrupt FIFO level select Register 0x34 read-write n 0x12 0xFFFFFFFF RXIFLSEL Receive interrupt FIFO level select 3 6 1/8 full Receive FIFO becomes greater than or equal to 1/8 full 0 1/4 full Receive FIFO becomes greater than or equal to 1/4 full 1 1/2 full Receive FIFO becomes greater than or equal to 1/2 full 2 3/4 full Receive FIFO becomes greater than or equal to 3/4 full 3 7/8 full Receive FIFO becomes greater than or equal to 7/8 full 4 TXIFLSEL Transmit interrupt FIFO level select 0 3 1/8 full Transmit FIFO becomes less than or equal to 1/8 full 0 1/4 full Transmit FIFO becomes less than or equal to 1/4 full 1 1/2 full Transmit FIFO becomes less than or equal to 1/2 full 2 3/4 full Transmit FIFO becomes less than or equal to 3/4 full 3 7/8 full Transmit FIFO becomes less than or equal to 7/8 full 4 UARTILPR IrDA low-power counter Register 0x20 read-write n 0x0 0xFFFFFFFF ILPDVSR 8-bit low-power divisor value 0 8 UARTIMSC Interrupt mask set/clear Register 0x38 read-write n 0x0 0xFFFFFFFF BEIM Break error interrupt mask 9 10 Clear Clears the mask 0 Set Sets the mask 1 CTSMIM nUARTCTS modem interrupt mask 1 2 Clear Clears the mask 0 Set Sets the mask 1 DCDMIM nUARTDCD modem interrupt mask 2 3 Clear Clears the mask 0 Set Sets the mask 1 DSRMIM nUARTDSR modem interrupt mask 3 4 Clear Clears the mask 0 Set Sets the mask 1 FEIM Framing error interrupt mask 7 8 Clear Clears the mask 0 Set Sets the mask 1 OEIM Overrun error interrupt mask 10 11 Clear Clears the mask 0 Set Sets the mask 1 PEIM Parity error interrupt mask 8 9 Clear Clears the mask 0 Set Sets the mask 1 RIMIM nUARTRI modem interrupt mask 0 1 Clear Clears the mask 0 Set Sets the mask 1 RTIM Receive timeout interrupt mask 6 7 Clear Clears the mask 0 Set Sets the mask 1 RXIM Receive interrupt mask 4 5 Clear Clears the mask 0 Set Sets the mask 1 TXIM Transmit interrupt mask 5 6 Clear Clears the mask 0 Set Sets the mask 1 UARTLCR_H Line control Register 0x2C read-write n 0x0 0xFFFFFFFF BRK Send break 0 1 EPS Even parity select 2 3 FEN Enable FIFOs 4 5 PEN Parity enable 1 2 SPS Stick parity select 7 8 STP2 Two stop bits select 3 4 WLEN Word length 5 7 UARTMIS Masked interrupt status Register 0x40 read-only n 0x0 0xFFFFFFFF BEMIS Break error masked interrupt status 9 1 CTSMMIS nUARTCTS modem masked interrupt status 1 1 DCDMMIS nUARTDCD modem masked interrupt status 2 1 DSRMMIS nUARTDSR modem masked interrupt status 3 1 FEMIS Framing error masked interrupt status 7 1 OEMIS Overrun error masked interrupt status 10 1 PEMIS Parity error masked interrupt status 8 1 RIMMIS nUARTRI modem masked interrupt status 0 1 RTMIS Receive timeout masked interrupt status 6 1 RXMIS Receive masked interrupt status 4 1 TXMIS Transmit masked interrupt status 5 1 UARTRIS Raw interrupt status Register 0x3C read-only n 0x0 0xFFFFFFFF BERIS Break error interrupt status 9 1 CTSRMIS nUARTCTS modem interrupt status 1 1 DCDRMIS nUARTDCD modem interrupt status 2 1 DSRRMIS nUARTDSR modem interrupt status 3 1 FERIS Framing error interrupt status 7 1 OERIS Overrun error interrupt status 10 1 PERIS Parity error interrupt status 8 1 RIRMIS nUARTRI modem interrupt status 0 1 RTRIS Receive timeout interrupt status 6 1 RXRIS Receive interrupt status 4 1 TXRIS Transmit interrupt status 5 1 UARTRSR Receive status register/error clear Register UARTECR 0x4 read-write n 0x0 0xFFFFFFFF BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 2 3 FE Framing error: Indicates the received character did not had a valid stop bit 0 1 OE Overrunerror: Indicates if data is received and the receive FIFO is already full 3 4 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 1 2 UART0_Secure UART 0 (Secure) UART 0x50101000 0x0 0x4C registers n UARTCR Control Register 0x30 read-write n 0x300 0xFFFFFFFF CTSEn CTS hardware flow control enable 15 16 Disable CTS hardware flow control is disabled 0 Enable CTS hardware flow control is enabled 1 DTR Data transmit ready 10 11 LBE Loop back enable 7 8 Disable Loop back mode is disabled 0 Enable Loop back mode is enabled 1 Out1 Complement of the UART Out1 12 13 Out2 Complement of the UART Out2 13 14 RTS Request to send 11 12 RTSEn RTS hardware flow control enable 14 15 Disable RTS hardware flow control is disabled 0 Enable RTS hardware flow control is enabled 1 RXE Receive enable 9 10 Disable Reception is disabled 0 Enable Reception is enabled 1 SIREN SIR enable 1 2 Disable SIR is disabled 0 Enable SIR is enabled 1 SIRLP IrDA SIR low power mode 2 3 Disable SIR low power mode is disabled 0 Enable SIR low power mode is enabled 1 TXE Transmit enable 8 9 Disable Transmission is disabled 0 Enable Transmission is enabled 1 UARTEN UART enable 0 1 Disable UART is disabled 0 Enable UART is enabled 1 UARTDMACR DMA control Register 0x48 read-write n 0x0 0xFFFFFFFF DMAONERR DMA on error 2 3 Disable DMA receive request outputs are enabled when the UART error interrupt is asserted 0 Enable DMA receive request outputs are disabled when the UART error interrupt is asserted 1 RXDMAE Receive DMA enable 0 1 Disable Receive DMA is disabled 0 Enable Receive DMA is enabled 1 TXDMAE Transmit DMA enable 1 1 Disable Transmit DMA is disabled 0 Enable Transmit DMA is enabled 1 UARTDR Data Register 0x0 read-write n 0x0 0xFFFFFFFF BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 10 11 Data Receive/Transmit data 0 8 FE Framing error: Indicates the received character did not had a valid stop bit 8 9 OE Overrun error: Indicates if data is received and the receive FIFO is already full 11 12 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 9 10 UARTFBRD Fractional baud rate Register 0x28 read-write n 0x0 0xFFFFFFFF BAUD_DIVINT The integer baud rate divisor 0 6 UARTFR Flag Register 0x18 read-only n 0x0 0xFFFFFFFF BUSY UART busy 3 4 CTS Clear to send 0 1 DCD Data carrier detect 2 3 DSR Data set ready 1 2 RI Ring indicator 8 9 RXFE Receive FIFO empty 4 5 RXFF Receive FIFO full 6 7 TXFE Transmit FIFO empty 7 8 TXFF Transmit FIFO full 5 6 UARTIBRD Integer baud rate Register 0x24 read-write n 0x0 0xFFFFFFFF BAUD_DIVINT The integer baud rate divisor 0 16 UARTICR Interrupt clear Register 0x44 write-only n 0x0 0xFFFFFFFF BEIC Break error interrupt clear, write 1 to clear, write 0 has no effect 9 1 CTSMIC nUARTCTS modem interrupt clear, write 1 to clear, write 0 has no effect 1 1 DCDMIC nUARTDCD modem interrupt clear, write 1 to clear, write 0 has no effect 2 1 DSRIC nUARTDSR modem interrupt clear, write 1 to clear, write 0 has no effect 3 1 FEIC Framing error interrupt clear, write 1 to clear, write 0 has no effect 7 1 OEIC Overrun error interrupt clear, write 1 to clear, write 0 has no effect 10 1 PEIC Parity error interrupt clear, write 1 to clear, write 0 has no effect 8 1 RIMIC nUARTRI modem interrupt clear, write 1 to clear, write 0 has no effect 0 1 RTIC Receive timeout interrupt clear, write 1 to clear, write 0 has no effect 6 1 RXIC Receive interrupt clear, write 1 to clear, write 0 has no effect 4 1 TXIC Transmit interrupt clear, write 1 to clear, write 0 has no effect 5 1 UARTIFLS Interrupt FIFO level select Register 0x34 read-write n 0x12 0xFFFFFFFF RXIFLSEL Receive interrupt FIFO level select 3 6 1/8 full Receive FIFO becomes greater than or equal to 1/8 full 0 1/4 full Receive FIFO becomes greater than or equal to 1/4 full 1 1/2 full Receive FIFO becomes greater than or equal to 1/2 full 2 3/4 full Receive FIFO becomes greater than or equal to 3/4 full 3 7/8 full Receive FIFO becomes greater than or equal to 7/8 full 4 TXIFLSEL Transmit interrupt FIFO level select 0 3 1/8 full Transmit FIFO becomes less than or equal to 1/8 full 0 1/4 full Transmit FIFO becomes less than or equal to 1/4 full 1 1/2 full Transmit FIFO becomes less than or equal to 1/2 full 2 3/4 full Transmit FIFO becomes less than or equal to 3/4 full 3 7/8 full Transmit FIFO becomes less than or equal to 7/8 full 4 UARTILPR IrDA low-power counter Register 0x20 read-write n 0x0 0xFFFFFFFF ILPDVSR 8-bit low-power divisor value 0 8 UARTIMSC Interrupt mask set/clear Register 0x38 read-write n 0x0 0xFFFFFFFF BEIM Break error interrupt mask 9 10 Clear Clears the mask 0 Set Sets the mask 1 CTSMIM nUARTCTS modem interrupt mask 1 2 Clear Clears the mask 0 Set Sets the mask 1 DCDMIM nUARTDCD modem interrupt mask 2 3 Clear Clears the mask 0 Set Sets the mask 1 DSRMIM nUARTDSR modem interrupt mask 3 4 Clear Clears the mask 0 Set Sets the mask 1 FEIM Framing error interrupt mask 7 8 Clear Clears the mask 0 Set Sets the mask 1 OEIM Overrun error interrupt mask 10 11 Clear Clears the mask 0 Set Sets the mask 1 PEIM Parity error interrupt mask 8 9 Clear Clears the mask 0 Set Sets the mask 1 RIMIM nUARTRI modem interrupt mask 0 1 Clear Clears the mask 0 Set Sets the mask 1 RTIM Receive timeout interrupt mask 6 7 Clear Clears the mask 0 Set Sets the mask 1 RXIM Receive interrupt mask 4 5 Clear Clears the mask 0 Set Sets the mask 1 TXIM Transmit interrupt mask 5 6 Clear Clears the mask 0 Set Sets the mask 1 UARTLCR_H Line control Register 0x2C read-write n 0x0 0xFFFFFFFF BRK Send break 0 1 EPS Even parity select 2 3 FEN Enable FIFOs 4 5 PEN Parity enable 1 2 SPS Stick parity select 7 8 STP2 Two stop bits select 3 4 WLEN Word length 5 7 UARTMIS Masked interrupt status Register 0x40 read-only n 0x0 0xFFFFFFFF BEMIS Break error masked interrupt status 9 1 CTSMMIS nUARTCTS modem masked interrupt status 1 1 DCDMMIS nUARTDCD modem masked interrupt status 2 1 DSRMMIS nUARTDSR modem masked interrupt status 3 1 FEMIS Framing error masked interrupt status 7 1 OEMIS Overrun error masked interrupt status 10 1 PEMIS Parity error masked interrupt status 8 1 RIMMIS nUARTRI modem masked interrupt status 0 1 RTMIS Receive timeout masked interrupt status 6 1 RXMIS Receive masked interrupt status 4 1 TXMIS Transmit masked interrupt status 5 1 UARTRIS Raw interrupt status Register 0x3C read-only n 0x0 0xFFFFFFFF BERIS Break error interrupt status 9 1 CTSRMIS nUARTCTS modem interrupt status 1 1 DCDRMIS nUARTDCD modem interrupt status 2 1 DSRRMIS nUARTDSR modem interrupt status 3 1 FERIS Framing error interrupt status 7 1 OERIS Overrun error interrupt status 10 1 PERIS Parity error interrupt status 8 1 RIRMIS nUARTRI modem interrupt status 0 1 RTRIS Receive timeout interrupt status 6 1 RXRIS Receive interrupt status 4 1 TXRIS Transmit interrupt status 5 1 UARTRSR Receive status register/error clear Register UARTECR 0x4 read-write n 0x0 0xFFFFFFFF BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 2 3 FE Framing error: Indicates the received character did not had a valid stop bit 0 1 OE Overrunerror: Indicates if data is received and the receive FIFO is already full 3 4 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 1 2 UART1 UART 1 UART 0x40102000 0x0 0x4C registers n UART_1 UART1 Interrupt 50 UARTCR Control Register 0x30 read-write n 0x300 0xFFFFFFFF CTSEn CTS hardware flow control enable 15 16 Disable CTS hardware flow control is disabled 0 Enable CTS hardware flow control is enabled 1 DTR Data transmit ready 10 11 LBE Loop back enable 7 8 Disable Loop back mode is disabled 0 Enable Loop back mode is enabled 1 Out1 Complement of the UART Out1 12 13 Out2 Complement of the UART Out2 13 14 RTS Request to send 11 12 RTSEn RTS hardware flow control enable 14 15 Disable RTS hardware flow control is disabled 0 Enable RTS hardware flow control is enabled 1 RXE Receive enable 9 10 Disable Reception is disabled 0 Enable Reception is enabled 1 SIREN SIR enable 1 2 Disable SIR is disabled 0 Enable SIR is enabled 1 SIRLP IrDA SIR low power mode 2 3 Disable SIR low power mode is disabled 0 Enable SIR low power mode is enabled 1 TXE Transmit enable 8 9 Disable Transmission is disabled 0 Enable Transmission is enabled 1 UARTEN UART enable 0 1 Disable UART is disabled 0 Enable UART is enabled 1 UARTDMACR DMA control Register 0x48 read-write n 0x0 0xFFFFFFFF DMAONERR DMA on error 2 3 Disable DMA receive request outputs are enabled when the UART error interrupt is asserted 0 Enable DMA receive request outputs are disabled when the UART error interrupt is asserted 1 RXDMAE Receive DMA enable 0 1 Disable Receive DMA is disabled 0 Enable Receive DMA is enabled 1 TXDMAE Transmit DMA enable 1 1 Disable Transmit DMA is disabled 0 Enable Transmit DMA is enabled 1 UARTDR Data Register 0x0 read-write n 0x0 0xFFFFFFFF BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 10 11 Data Receive/Transmit data 0 8 FE Framing error: Indicates the received character did not had a valid stop bit 8 9 OE Overrun error: Indicates if data is received and the receive FIFO is already full 11 12 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 9 10 UARTFBRD Fractional baud rate Register 0x28 read-write n 0x0 0xFFFFFFFF BAUD_DIVINT The integer baud rate divisor 0 6 UARTFR Flag Register 0x18 read-only n 0x0 0xFFFFFFFF BUSY UART busy 3 4 CTS Clear to send 0 1 DCD Data carrier detect 2 3 DSR Data set ready 1 2 RI Ring indicator 8 9 RXFE Receive FIFO empty 4 5 RXFF Receive FIFO full 6 7 TXFE Transmit FIFO empty 7 8 TXFF Transmit FIFO full 5 6 UARTIBRD Integer baud rate Register 0x24 read-write n 0x0 0xFFFFFFFF BAUD_DIVINT The integer baud rate divisor 0 16 UARTICR Interrupt clear Register 0x44 write-only n 0x0 0xFFFFFFFF BEIC Break error interrupt clear, write 1 to clear, write 0 has no effect 9 1 CTSMIC nUARTCTS modem interrupt clear, write 1 to clear, write 0 has no effect 1 1 DCDMIC nUARTDCD modem interrupt clear, write 1 to clear, write 0 has no effect 2 1 DSRIC nUARTDSR modem interrupt clear, write 1 to clear, write 0 has no effect 3 1 FEIC Framing error interrupt clear, write 1 to clear, write 0 has no effect 7 1 OEIC Overrun error interrupt clear, write 1 to clear, write 0 has no effect 10 1 PEIC Parity error interrupt clear, write 1 to clear, write 0 has no effect 8 1 RIMIC nUARTRI modem interrupt clear, write 1 to clear, write 0 has no effect 0 1 RTIC Receive timeout interrupt clear, write 1 to clear, write 0 has no effect 6 1 RXIC Receive interrupt clear, write 1 to clear, write 0 has no effect 4 1 TXIC Transmit interrupt clear, write 1 to clear, write 0 has no effect 5 1 UARTIFLS Interrupt FIFO level select Register 0x34 read-write n 0x12 0xFFFFFFFF RXIFLSEL Receive interrupt FIFO level select 3 6 1/8 full Receive FIFO becomes greater than or equal to 1/8 full 0 1/4 full Receive FIFO becomes greater than or equal to 1/4 full 1 1/2 full Receive FIFO becomes greater than or equal to 1/2 full 2 3/4 full Receive FIFO becomes greater than or equal to 3/4 full 3 7/8 full Receive FIFO becomes greater than or equal to 7/8 full 4 TXIFLSEL Transmit interrupt FIFO level select 0 3 1/8 full Transmit FIFO becomes less than or equal to 1/8 full 0 1/4 full Transmit FIFO becomes less than or equal to 1/4 full 1 1/2 full Transmit FIFO becomes less than or equal to 1/2 full 2 3/4 full Transmit FIFO becomes less than or equal to 3/4 full 3 7/8 full Transmit FIFO becomes less than or equal to 7/8 full 4 UARTILPR IrDA low-power counter Register 0x20 read-write n 0x0 0xFFFFFFFF ILPDVSR 8-bit low-power divisor value 0 8 UARTIMSC Interrupt mask set/clear Register 0x38 read-write n 0x0 0xFFFFFFFF BEIM Break error interrupt mask 9 10 Clear Clears the mask 0 Set Sets the mask 1 CTSMIM nUARTCTS modem interrupt mask 1 2 Clear Clears the mask 0 Set Sets the mask 1 DCDMIM nUARTDCD modem interrupt mask 2 3 Clear Clears the mask 0 Set Sets the mask 1 DSRMIM nUARTDSR modem interrupt mask 3 4 Clear Clears the mask 0 Set Sets the mask 1 FEIM Framing error interrupt mask 7 8 Clear Clears the mask 0 Set Sets the mask 1 OEIM Overrun error interrupt mask 10 11 Clear Clears the mask 0 Set Sets the mask 1 PEIM Parity error interrupt mask 8 9 Clear Clears the mask 0 Set Sets the mask 1 RIMIM nUARTRI modem interrupt mask 0 1 Clear Clears the mask 0 Set Sets the mask 1 RTIM Receive timeout interrupt mask 6 7 Clear Clears the mask 0 Set Sets the mask 1 RXIM Receive interrupt mask 4 5 Clear Clears the mask 0 Set Sets the mask 1 TXIM Transmit interrupt mask 5 6 Clear Clears the mask 0 Set Sets the mask 1 UARTLCR_H Line control Register 0x2C read-write n 0x0 0xFFFFFFFF BRK Send break 0 1 EPS Even parity select 2 3 FEN Enable FIFOs 4 5 PEN Parity enable 1 2 SPS Stick parity select 7 8 STP2 Two stop bits select 3 4 WLEN Word length 5 7 UARTMIS Masked interrupt status Register 0x40 read-only n 0x0 0xFFFFFFFF BEMIS Break error masked interrupt status 9 1 CTSMMIS nUARTCTS modem masked interrupt status 1 1 DCDMMIS nUARTDCD modem masked interrupt status 2 1 DSRMMIS nUARTDSR modem masked interrupt status 3 1 FEMIS Framing error masked interrupt status 7 1 OEMIS Overrun error masked interrupt status 10 1 PEMIS Parity error masked interrupt status 8 1 RIMMIS nUARTRI modem masked interrupt status 0 1 RTMIS Receive timeout masked interrupt status 6 1 RXMIS Receive masked interrupt status 4 1 TXMIS Transmit masked interrupt status 5 1 UARTRIS Raw interrupt status Register 0x3C read-only n 0x0 0xFFFFFFFF BERIS Break error interrupt status 9 1 CTSRMIS nUARTCTS modem interrupt status 1 1 DCDRMIS nUARTDCD modem interrupt status 2 1 DSRRMIS nUARTDSR modem interrupt status 3 1 FERIS Framing error interrupt status 7 1 OERIS Overrun error interrupt status 10 1 PERIS Parity error interrupt status 8 1 RIRMIS nUARTRI modem interrupt status 0 1 RTRIS Receive timeout interrupt status 6 1 RXRIS Receive interrupt status 4 1 TXRIS Transmit interrupt status 5 1 UARTRSR Receive status register/error clear Register UARTECR 0x4 read-write n 0x0 0xFFFFFFFF BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 2 3 FE Framing error: Indicates the received character did not had a valid stop bit 0 1 OE Overrunerror: Indicates if data is received and the receive FIFO is already full 3 4 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 1 2 UART1_Secure UART 1 (Secure) TPU 0x50102000 0x0 0x400 registers n PRNG_RND_NUM PRNG Random Number Output 0x4 read-write n 0x0 0xFFFFFFFF PRNG_USER_ENTROPY PRNG User Entropy Value 0x0 read-write n 0x0 0xFFFFFFFF WATCHDOG Non-secure Watchdog Timer Watchdog 0x40081000 0x0 0xC04 registers n NONSEC_WATCHDOG Non-Secure Watchdog Interrupt 1 WDOGCONTROL Watchdog Control Register 0x8 read-write n 0x0 0xFFFFFFFF INTEN Enable the interrupt event 0 1 Disable Disable Watchdog Interrupt 0 Enable Enable Watchdog interrupt 1 RESEN Enable watchdog reset output 1 2 Disable Disable Watchdog reset 0 Enable Enable Watchdog reset 1 WDOGINTCLR Watchdog Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear WDOGLOAD Watchdog Load Register 0x0 read-write n 0xFFFFFFFF 0xFFFFFFFF WDOGLOCK Watchdog Lock Register 0xC00 read-write n 0x0 0xFFFFFFFF Access Enable register writes 1 32 Status Register write enable status 0 1 Enabled Write access to all other registers is enabled. This is the default 0 Disabled Write access to all other registers is disabled 1 WDOGMIS Watchdog Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Watchdog Interrupt 0 1 WDOGRIS Watchdog Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw watchdog Interrupt 0 1 WDOGVALUE Watchdog Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF WATCHDOG_Secure Watchdog (Secure) Watchdog 0x50081000 0x0 0xC04 registers n WDOGCONTROL Watchdog Control Register 0x8 read-write n 0x0 0xFFFFFFFF INTEN Enable the interrupt event 0 1 Disable Disable Watchdog Interrupt 0 Enable Enable Watchdog interrupt 1 RESEN Enable watchdog reset output 1 2 Disable Disable Watchdog reset 0 Enable Enable Watchdog reset 1 WDOGINTCLR Watchdog Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear WDOGLOAD Watchdog Load Register 0x0 read-write n 0xFFFFFFFF 0xFFFFFFFF WDOGLOCK Watchdog Lock Register 0xC00 read-write n 0x0 0xFFFFFFFF Access Enable register writes 1 32 Status Register write enable status 0 1 Enabled Write access to all other registers is enabled. This is the default 0 Disabled Write access to all other registers is disabled 1 WDOGMIS Watchdog Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Watchdog Interrupt 0 1 WDOGRIS Watchdog Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw watchdog Interrupt 0 1 WDOGVALUE Watchdog Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF